Array substrate, sub-region driving method of array substrate, display module and display device

Abstract

The invention provides an array substrate, a sub-region driving method of the array substrate, a display module and a display device. The display region of the array substrate includes at least two sub-regions; the array substrate includes second gate electrodes and first gate electrodes; according to the normal timing sequence, first voltage allowing thin film transistors to be switched on is input to each first gate electrode, and at the same time, second voltage allowing all the thin film transistors in at least one of the sub-regions to be switched off is input to all the second gate electrodes in the at least one of the sub-regions. According to the array substrate, a mode of achieving panel sub-region driving is simpler, the situation that delayed differentiation occurs between every two gate lines in each sub-region can be improved, and the risk of nonuniform regional brightness is thus reduced.

Description

technical field [0001] The present invention relates to the technical field of display device processing, and in particular, to an array substrate and a partition driving method thereof, a display module and a display device. Background technique [0002] Thin-film transistor (TFT for short) is one of the types of field-effect transistors, which includes source (Source Electrode), drain (Drain Electrode) and active area (Active Area), where the source and data The drain is connected to the pixel electrode; the gate is connected to the gate line; the active region is made of semiconductor material, which is usually amorphous silicon, polysilicon, metal oxide semiconductor, etc. [0003] In practical applications, in order to reduce the power consumption of the display panel, the resolution and refresh rate of the display panel can be controlled partitionally. Reduce the resolution and refresh rate of the display. like figure 1 As shown in FIG. 2 , it is a schematic partiti...

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Problems solved by technology

[0004] However, since an additional set of GOA circuits 11 is added to the above-mentioned array substrate, and the jumper connection between the fifth partition 5 and the output terminal of the GOA needs to be added, this not only increases the difficulty of the process and the complexity of the panel design, but also increases the cost. , and it is easy to generate delay differences between the gate lines of each partition, resulting in uneven brightness in the area (blogmura)

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