Method for realizing voltage regulation by digital low dropout voltage regulator and digital low dropout voltage regulator

A low-dropout voltage regulator, digital technology, applied in the method and digital low-dropout voltage regulator, the digital low-dropout voltage regulator realizes the field of voltage regulation, and can solve the problem of increasing the start-up time of D-LDO and reducing the response of D-LDO output voltage speed and other issues to achieve the effect of reducing the time required for stabilization, reducing the ringing phenomenon, and shortening the startup time

Active Publication Date: 2018-03-02
BOE TECH GRP CO LTD +1
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Problems solved by technology

That is to say, due to the ringing phenomenon, the D-LDO will go through multiple oscillations at the output end to achieve a stable output. In this way, the response speed of the D-LDO output voltage is seriously reduced, making the D-LDO take longer to achieve output voltage stabilization, thereby increasing the startup time of the D-LDO

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  • Method for realizing voltage regulation by digital low dropout voltage regulator and digital low dropout voltage regulator
  • Method for realizing voltage regulation by digital low dropout voltage regulator and digital low dropout voltage regulator
  • Method for realizing voltage regulation by digital low dropout voltage regulator and digital low dropout voltage regulator

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[0031] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0032] Whether it can quickly achieve output stability is an important indicator of D-LDO design. In order to solve the problem of the slow response speed of the output voltage of the D-LDO, the inventor of the present application proposes: using the relationship between the change of the output voltage of the D-LDO and the numerical change of the conduction of the PMOS transistor during the start-up process, to obtain the stable output of the output voltage The conduction value of the PMOS transistor can be directly controlled according to the obtained value of the PMOS tran...

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Abstract

The invention discloses a voltage stabilization implementing method for a digital low voltage difference voltage stabilizer, and the digital low voltage difference voltage stabilizer. The method includes: acquiring two or more first numerical values for controlling a transistor turn-on number when the output voltage and the reference voltage are equal for continuous twice or more; calculating a second numerical value for controlling the transistor turn-on number when the output voltage is stable according to the acquired two or more first numerical values; and using the second numerical value to control the transistor turn-on number of the digital low voltage difference voltage stabilizer. In the technical scheme, the second numerical value controls the transistor turn-on number to be close to the numerical value when the output voltage is stable, and in this way, the D-LDO output voltage can be rapidly stabilized, the response speed of the D-LDO output voltage is improved, the D-LDO can rapidly achieve stabilized output voltage, the stabilization time of the D-LDO is shortened, the starting time of the D-LDO is shortened, and ringing can be reduced to some extent.

Description

technical field [0001] The invention relates to but not limited to power management technology, especially a digital low-dropout voltage stabilizer and a method for realizing voltage stabilization and the digital low-dropout voltage stabilizer. Background technique [0002] Low Dropout Regulator (LDO, Low Dropout Regulator) voltage regulator as a power management circuit has been widely used in portable electronic devices, wireless energy transmission systems and other fields. figure 1 It is a schematic diagram of a circuit principle of a digital LDO (D-LDO) in the related art, such as figure 1 As shown, the output voltage Vout is compared with the reference voltage Vref and then output to the counter to control the increase or decrease of the counter value. The counter transmits the value to the decoder, and the decoder controls the P-channel metal oxide semiconductor through the decoded information. The conduction number of the (PMOS) transistor array controls the output ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05F1/56
CPCG05F1/56
Inventor 冯雪欢李永谦徐攀胡琪张星栾梦雨
Owner BOE TECH GRP CO LTD
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