A low dropout linear regulator circuit
A low-dropout linear, voltage-stabilizing circuit technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve problems such as complex LDO structures, and achieve the effect of easy integration and simple feedback structure
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[0021] The present invention will be described in detail below in conjunction with the accompanying drawings.
[0022] figure 2 Shown is a schematic diagram of the LDO structure of the present invention.
[0023] The working principle of the present invention is:
[0024] When the enable end EN is abnormal (that is, the enable end is at a low level), the first PMOS transistor MP1 is turned on, so that the second PMOS transistor MP2 is turned off, and a low level signal is output.
[0025] When the enable terminal EN is normal (that is, the enable terminal is at a high level), the current I1 flowing through the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 will be mirrored to the sixth NMOS transistor MN6 generates current I4 and the eleventh NMOS transistor MN11 generates current I2, since the width-to-length ratio of the sixth NMOS transistor MN6 is twice that of the third NMOS transistor MN3, so
[0026]
[0027] Current I...
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