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Cache management method and device

A cache management and caching technology, applied in the field of data communication, can solve problems such as occupying a large shared cache, discarding non-congested flow packets, etc.

Inactive Publication Date: 2017-06-30
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, when the on-chip eDRAM is used as the shared cache architecture, the actual cache capacity will be smaller than the actual cache capacity of the traditional DDR as the shared cache architecture. At present, for the management of the shared cache, there will be problems when some streams are congested. When , the congested flow will occupy more shared buffers. When the shared buffer occupied by the congested flow reaches a certain threshold, the non-congested flow packets will be discarded.

Method used

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  • Cache management method and device

Examples

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Embodiment 1

[0064] See figure 1 , Which shows the flow of a cache management method provided by an embodiment of the present invention, the method may be applied to a cache management apparatus, and the method may include:

[0065] S101: Obtain message granularity information corresponding to the descriptor of the received message;

[0066] It should be noted that the descriptor of the received message can be obtained by parsing the received message, which can specifically include: the service type (TC, Traffic Class) of the received message, the queue number of the queue where the received message is located, and the The identifier of the target chip corresponding to the transmission of the received message, etc. This embodiment of the present invention will not repeat this. It is understandable that different descriptors can be used to indicate the message granularity information corresponding to the received message, for example, when the received message When the descriptor of the received...

Embodiment 2

[0099] Based on the same technical idea as the foregoing embodiment, see Image 6 , Which shows a cache management device 60 provided by an embodiment of the present invention. The device 60 may include: an acquiring unit 601 and a determining unit 602; wherein,

[0100] The acquiring unit 601 is configured to acquire the message granularity information corresponding to the descriptor of the received message;

[0101] The determining unit 602 is configured to determine a discarding processing operation for the received message through the message discarding mechanism corresponding to the message granularity information.

[0102] Exemplarily, when the descriptor of the received message is the service type TC of the received message, the message granularity information is used to characterize that the received message is a stream-level or intermediate-level message;

[0103] Correspondingly, the determining unit 602 is specifically configured to: when the sum of the length of the receive...

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PUM

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Abstract

The embodiment of the invention discloses a cache management method and device. The method comprises the steps of obtaining message particle size information corresponding to a descriptor of a receiving message; and determining to carry out discarding processing operation on the receiving message according to a message discharging mechanism corresponding to the message particle size information. According to the method, combined use is carried out on various cache management mechanisms according to processing particle sizes and relatively high cache use efficiency can be ensured in various application scenes, thereby carrying out efficient management on a cache.

Description

Technical field [0001] The present invention relates to data communication technology, in particular to a method and device for cache management. Background technique [0002] With the explosive increase of network bandwidth, the traditional double-rate synchronous dynamic random access memory (DDR, Double Data Rate) as the shared cache architecture will lead to a sharp increase in the number of DDR chip pins when the bandwidth is increased, thereby greatly increasing This reduces the difficulty of packaging and single board production. [0003] At present, a high-density on-chip enhanced dynamic random access memory (eDRAM, enhanced Dynamic Random Access Memory) is usually used for a grouped parallel architecture as a shared cache architecture, so that when the cache access bandwidth increases, there is no need to increase chip pins. [0004] However, when the on-chip eDRAM is used as the shared cache architecture, the actual cache capacity will be smaller than the actual cache cap...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/08
CPCH04L67/568H04L67/61H04L69/40
Inventor 王林滨
Owner SANECHIPS TECH CO LTD