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Area-optimized retention flop implementation

A flip-flop, planar technology, applied in the direction of electric pulse generator circuit, electric solid device, semiconductor device, etc.

Active Publication Date: 2017-07-07
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The p-well plane includes p-type semiconductor material

Method used

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  • Area-optimized retention flop implementation
  • Area-optimized retention flop implementation
  • Area-optimized retention flop implementation

Examples

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Embodiment Construction

[0019] Example embodiments are described with reference to the drawings, wherein like reference numerals are used to indicate similar or equivalent elements. The illustrated order of acts or events should not be considered limiting, as some acts or events may occur in a different order and / or concurrently with other acts or events. Furthermore, some of the illustrated acts or events may not be required to implement a methodology in accordance with the present disclosure.

[0020] Figure 5 is a schematic diagram of a quadruple-height logic cell 500 occupying four adjacent cell rows 510, 512, 514, 516 in accordance with an exemplary aspect of the present disclosure. Figure 5 Two substantially parallel n-well rows 520 and 540 disposed on p-well plane 505 are shown. The p-well plane 505 includes a positively doped (p+) semiconductor material. N-well rows or n-well patterns 520 and 540 each include a layer of negatively doped (n+) semiconductor material deposited on top of p-w...

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PUM

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Abstract

The invention relates to area-optimized retention flop implementation, and discloses an integrated circuit device. The integrated circuit device includes a p-well plane (505), a plurality of substantially parallel n-well rows (520,540), and a logic cell (500). The p-well plane (505) is comprised of p-type semiconductor material. Each n-well row (520,540) comprises an n-type layer disposed on the surface of the p-well plane (505). The plurality of n-well rows (520,540) includes a first n-well row (520) and a second n-well row (540). The logic cell (500) is arranged on the p-well plane (505) and the footprint of the logic cell encompasses both the first and second n-well rows (520,540).

Description

Background technique [0001] With the ever-increasing demand for increased battery life of battery powered devices, the demand for low power systems and SOCs (systems on a chip) is also increasing. This leads to the need for power management designs with multiple power / voltage domains. In designs with power domains, it is often desirable to preserve state (of flip-flops) even when the power domain is switched off. This state is often referred to as a standby state and helps reduce power down and power up times. To preserve this state, hold flip-flops are widely used in almost all power management SOCs. [0002] A typical retention flip-flop includes a master latch and a slave latch, where the slave latch stores the state during power down. The slave latch of a holding flip-flop must be powered by an always-on (AON) holding supply to store data while the associated device is off. The n-well and drain of the slave latch must be connected to an always-on power supply. To redu...

Claims

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Application Information

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IPC IPC(8): H03K3/027
CPCH03K3/027H03K3/35625H01L27/0207H01L27/088H01L29/1095H03K3/3562
Inventor S·C·斯里瓦斯塔瓦V·辛格哈尔
Owner TEXAS INSTR INC