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A non-contact and non-destructive method for measuring the resistivity of epitaxial SOI epitaxial layer

An epitaxial layer, non-damage technology, applied in the direction of semiconductor/solid-state device testing/measurement, circuits, electrical components, etc., can solve problems such as damage, product scrapping, etc., and achieve the effect of improving product yield and saving costs

Active Publication Date: 2020-03-20
SHENYANG SILICON TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, Hg-CV is measured at the time of contact, which is a destructive measurement. In actual production, the product must be scrapped after measurement
And Hg is a metal pollutant, once it pollutes the workshop, it will cause irreversible and serious consequences

Method used

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  • A non-contact and non-destructive method for measuring the resistivity of epitaxial SOI epitaxial layer
  • A non-contact and non-destructive method for measuring the resistivity of epitaxial SOI epitaxial layer
  • A non-contact and non-destructive method for measuring the resistivity of epitaxial SOI epitaxial layer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] The original silicon wafer is 8 inches, P type, lattice direction (100), resistance value 8.5-11.5ohm / cm, surface coverage Silicon dioxide (SiO2), polished on one side, dosed at 4.0×10 16 / cm 2 , the implantation energy is 200KeV, hydrogen molecular ions (H 2 + )injection. The substrate silicon wafer is P-type, the lattice direction is (100), the resistivity is 8.5-11.5ohm-cm, and the silicon wafer is polished on one side. Two silicon wafers were bonded into a bonded structure by plasma-enhanced bonding at room temperature, placed in a commercially adjustable temperature microwave oven, and annealed at a transition temperature of 200°C for 15 minutes, and then immediately at this temperature With 2.45GHz frequency, 1000W output power, after 15 minutes of microwave radiation, the film with an average thickness of 0.6452μm is peeled off, and the top layer is formed after CMP treatment SOI wafer material.

[0044] A P-type epitaxial layer is epitaxially layered on ...

Embodiment 2

[0055] The original silicon wafer is 8 inches, N type, lattice direction (100), resistance value 8.5-11.5ohm / cm, surface coverage Silicon dioxide (SiO 2 ), polished on one side, after a dose of 4.0×10 16 / cm 2 , the implantation energy is 200KeV, hydrogen molecular ions (H 2 + )injection. The substrate silicon wafer is N-type, the crystal lattice direction is (100), the resistivity is 8.5-11.5ohm-cm, and the silicon wafer is polished on one side. Two silicon wafers were bonded into a bonded structure by plasma-enhanced bonding at room temperature, placed in a commercially adjustable temperature microwave oven, and annealed at a transition temperature of 200°C for 15 minutes, and then immediately at this temperature With 2.45GHz frequency, 1000W output power, after 15 minutes of microwave radiation, the film with an average thickness of 0.6452μm is peeled off, and the top layer is formed after CMP treatment SOI wafer material. An N-type epitaxial layer is epitaxially d...

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Abstract

The invention discloses a non-contact and no-damage epitaxial SOI epitaxial layer electrical resistivity measurement method. The method is specific to the epitaxial SOI epitaxial layer electrical resistivity measurement; for achieving an accurate measurement effect, the epitaxial SOI surface is subjected to specific pretreatment to enable surface defects and electrical parameters to satisfy requirements; then a specific voltage is applied, and the electrical resistivity is worked out according to a C-V curve; and the final result error is less than 0.1%. The method is non-contact type measurement, and has the advantages of no destruction, no damage, reutilization and the like; in actual production, the measured epitaxial SOI still can be used; and therefore, the product yield can be greatly improved, and cost can be saved.

Description

technical field [0001] The invention relates to the technical field of measuring the resistivity of an epitaxial layer of an epitaxial SOI (Silicon on Insulator, silicon on insulator), in particular to a non-contact and non-damaging method for measuring the resistivity of an epitaxial SOI epitaxial layer. Background technique [0002] TM-SOI is a kind of SOI technology based on the ion implantation stripping method (smart-cut method). The "TM-SOI smart-cut method" has applied for an invention patent in China with the application number 200310123080.1, and has obtained the invention patent authorization from the China Patent Office. The specific method: form an oxide film on at least one of the two silicon wafers, and use ion implantation to form an ion separation layer in the thin film of one of the silicon wafers, so that the ion-implanted surface is separated from the oxide film. The film is bonded to the other silicon wafer at room temperature to form a bonded body. Then...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/14
Inventor 付超凡柳清超高文琳
Owner SHENYANG SILICON TECH