Integrated Analog Delay Line for Pulse Width Modulator

Abstract

The present invention relates to integrated analog delay lines for pulse width modulators. A pulse width modulation (PWM) system includes analog and digital components. The analog component introduces an offset (ie, a time delay) to the analog signal received at the input in the analog (continuous time) domain with tuning operations fine-tuned in the analog signal. The analog components include an analog delay line comprising a plurality of analog delay components configured to introduce a time delay to the analog signal based on a model of the transmission line.

Description

Background technique

[0001] An all-digital solution for modern wireless communication systems brings significant benefits in terms of flexibility, reconfigurability, and reduced power consumption. Pulse Width Modulation (PWM) may be important for implementing such a system. The phase shift block is the core element used to perform phase or time shift operations in PWM hardware. State-of-the-art nm-scale CMOS technologies exhibit gate delays of a few ps. This time delay resolution is directly related to the dynamic range performance of the transmitter system, similar to the number of bits in an analog-to-digital A / D converter or digital-to-analog D / A converter. To further reduce the resolution step size, very expensive modern detail point CMOS technology is often used and simpler, less expensive components are required. Contents of the invention

[0002] The present invention provides a hybrid analog-to-digital pulse width modulation (PWM) system comprising: PWM means comp...

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