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Methods and circuits for deadlock avoidance

A circuit and communication circuit technology, applied in the field of data communication

Active Publication Date: 2017-08-29
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, implementing an appropriate arrangement for communication between the different parts presents a challenge to the designer

Method used

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  • Methods and circuits for deadlock avoidance
  • Methods and circuits for deadlock avoidance
  • Methods and circuits for deadlock avoidance

Examples

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Embodiment Construction

[0016] Programmable ICs may include circuits that communicate data using different communication protocols, respectively. For example, the programmable IC may use the AXI communication protocol to transfer data between different parts of the system on a first bus, and the PCIe communication protocol to communicate with external devices connected to I / O ports of the system. When communicating data between circuits using different communication protocols, interface circuits may be used to convert data between the data formats used by each protocol.

[0017] However, due to the ordering rules utilized by the different communication protocols, a deadlock situation may occur in which each communication circuit requires data from the other communication circuit before the communication circuit can continue processing. For example, a deadlock can occur when a data channel from an AXI device to a PCIe device becomes blocked by an unreported write. Non-reported writes require the rece...

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Abstract

A system is disclosed that includes a first communication circuit (110) that communicates data (302,304) over a first data port (112) using a first communication protocol. The system also includes a second communication circuit (130, 340) that communicates data over a second data port (132) using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit (120,310) is configured to communicate data between the first data port (112) of the first communication circuit and the second data port (132) of the second communication circuit. The bridge circuit (120,310) is configured to communicate non-posted writes to the second communication circuit via a buffer circuit (122,328) and communicate posted writes to the second communication circuit via a communication path (322) that bypasses the buffer circuit.

Description

technical field [0001] The present disclosure relates generally to integrated circuits (ICs) and, more particularly, to data communications. Background technique [0002] Programmable integrated circuits (ICs) are devices that can be programmed to perform specific logic functions. One type of programmable IC - a field programmable gate array (FPGA) - usually includes an array of programmable chips. Each programmable slice may include programmable interconnect and programmable logic. Programmable interconnects typically include a large number of interconnect lines of various lengths interconnected by programmable interconnect points (PIPs). Programmable logic implements user-designed logic through the use of programmable elements that may include, for example, function generators, registers, arithmetic logic, and the like. Programmable interconnect and programmable logic are typically programmed by loading configuration data streams into internal configuration memory cells...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F13/40G06F13/42G06F12/0804G06F12/0831G06F12/0888
CPCG06F12/0804G06F12/0833G06F12/0888G06F13/1642G06F13/1673G06F13/4036G06F13/4282Y02D10/00
Inventor S·艾哈迈德T·克诺普
Owner XILINX INC
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