Static memory device and static memory cell thereof

Abstract

The invention relates to a static memory device and a static memory cell thereof. The static memory cell comprises a data latch circuit, a data write circuit and a data readout circuit, wherein the data latch circuit comprises a first-third state output inverting circuit and a second-third state output inverting circuit, the data write circuit provides a first reference voltage as the power supply receiving terminal of the selected three-state output inverting circuit of one of the first-third state output inverting circuit and the second-third state output inverting circuit in a data write time period, and provides a second reference voltage to the input terminal of the selected three-state output inverting circuit, and the data readout circuit produces readout data in a data readout time period according to the voltage at the output terminal of the second-third state output inverting circuit and the second reference voltage.

Description

technical field [0001] The invention relates to a static memory cell, and in particular to a static memory cell capable of eliminating write disturbance. Background technique [0002] With the advancement of semiconductor technology, consumer electronics products have become an essential tool in people's lives. Among them, in electronic products, memory devices play an important role, such as static random access memory. [0003] Today, as the semiconductor process technology is becoming more and more sophisticated, as the minimum size of the process is gradually reduced, the write margin and the minimum operating voltage of the SRAM are more and more strictly restricted. Therefore, in the SRAM During the access action of writing or reading data of the static memory cells in the memory, the half-selected static memory cells may generate read and write disturbances, resulting in leakage and data loss. Therefore, it is an important task for those skilled in the art to design...

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Problems solved by technology

[0003] Today, as the semiconductor process technology is becoming more and more sophisticated, as the minimum size of the process is gradually reduced, the write margin and the minimum operating voltage of the SRAM are more and more strictly restricted. Therefore, in the SRAM When the data is written or read from the static memory cell in the memory, the half-selected static memory cell may cause read or write interference, which may cause leakage and data loss.

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