A data reading circuit

Abstract

An embodiment of the present invention discloses a data reading circuit, which is applied to a second clock domain. The first clock domain sends data to the second clock domain and sends an associated clock signal at the same time. It is characterized in that the data reading circuit includes a phase difference A determination module, a delay detection module and a read control module, the phase difference determination module is connected to the clock signal associated with the channel and the clock signal of the second clock domain, wherein: the phase difference determination module is used to determine the clock signal associated with the channel and the second clock domain. The phase difference between the clock signals; the delay detection module is used to detect the delay value of the data transmitted from the buffer to the trigger; the read control module is used to determine the trigger can read according to the phase difference and the delay value. The trigger edge of the clock signal of the second clock domain of the data output from the buffer. By adopting the present invention, the phase difference between the clock signal associated with the channel and the clock signal of the local domain can be determined, thereby realizing data reading.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a data reading circuit. Background technique [0002] Source synchronization technology is a low-latency cross-clock domain synchronization technology, which is mainly used in the data interaction process between clock domains with the same source and frequency but different phases. Its main technical principle is: the first clock domain sends data to the second clock domain while sending the associated clock signal (that is, the clock signal of the first clock domain), the second clock domain writes data according to the associated clock signal, and then The written data is read according to the clock signal of this domain (that is, the clock signal of the second clock domain). The specific implementation process can be as follows figure 1 As shown, the first clock domain sends data and the associated clock signal to the second clock domain at the same time, and the FIFO (...

AI Technical Summary

Problems solved by technology

However, adopting the method of the Data Sync signal requires an additional I / O (Input / Output, input / output) interface for transmitting the Data Sync signal, which increases the overhead of the hardware. Strictly maintain the phase relationship between the Data Sync signal and data, which increases the difficulty in implementation

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