Dram circuit provided with a built-in processor

Abstract

The invention relates to a memory circuit comprising: a memory network comprising at least one memory bank (418); a first processor (420); and a processor control interface for receiving instructions for processing data addressed to the first processor from a central processor (P1, P2), the processor control interface being designed to indicate to the central processor when the first processor has finished accessing at least one memory bank of the memory network, said memory banks becoming accessible for the central processor.

Description

technical field [0001] This disclosure relates to the field of DRAM (Dynamic Random Access Memory) circuits with integrated processors and methods of communicating with such memories. Background technique [0002] Modern computers typically include processing circuitry coupled to one or more dynamic random access memory (DRAM) circuits and are typically implemented as a system on a chip (SoC). Such memory, which typically requires periodic refresh operations, is dense and relatively fast to access and is therefore used as main RAM data storage in most computers. However, due to the ever-increasing amount of data to be transferred between the SoC and the DRAM circuits, such data transfers tend to slow down the operation of the computer and result in relatively high power consumption. [0003] A solution that has been proposed is to provide, in addition to the processor in the Soc, a DRAM circuit in which one or more processors are integrated. Such a solution reduces the lev...

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Problems solved by technology

[0006] A problem in systems such as described in publication WO2010 / 141221 is that the external processor incorporating the memory controller must be modified to allow arbitration control signals to be passed to and from the internal controller, which leads to the solution expensive and complicated

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