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Memory direct access control device

A technology of access control and memory, applied in the direction of instrumentation, electrical digital data processing, etc.

Pending Publication Date: 2017-10-27
ROBERT BOSCH GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The problem underlying the invention is solved by a direct memory access control device according to claim 1 and by a method according to the dependent claims

Method used

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Examples

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Embodiment Construction

[0050] figure 1 A very simplified block circuit diagram of the computer system 10 is schematically shown. The computer system 10 has a computing unit 20, a working memory 30, a memory direct access control device 40, and a communication module 50. The computing unit 20, a working memory 30. The memory direct access control device 40 and the communication module 50 are connected to the bus system 12 respectively. Also like one or more of the components 20, 30, 40, 50, the bus system 12 may be arranged on a semiconductor device ("chip" or "Network on Chip"), for example. Supplementally, the memory direct access control device 40 includes configuration data 42, which is described in figure 2 It is further elaborated in.

[0051] figure 2 Shows something similar to figure 1 The computer system 10 in this case includes a computing unit 20, which has a large number of processor cores 20_1 to 20_n and working memory units 30_1 allocated to the processor cores 20_1 to 20_n, respectivel...

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PUM

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Abstract

The invention relates to a memory direct access control device (40), wherein the memory direct access control device (40) has a connection for connecting the memory direct access control device (40) to a bus system (12) connecting a plurality of bus users (60). In this case, the memory direct access control device (40) is designed to carry out the following steps: - receiving (102) at least two request signals (14) from different bus subscribers (60) for carrying out a data transfer from the relevant bus subscriber (60) to at least one further bus subscriber (60). Determining (104) an order for the data transmissions from the different bus subscribers (60) to the at least one further bus subscriber (60) as a function of a configuration data (42) characterizing a priority for the respective data transmission, executing (106) the data transmissions from the various bus users (60) to the at least one further bus subscriber (60) in the determined order using at least one memory direct access via the bus system (12).

Description

Technical field [0001] The invention relates to a memory direct access control device according to the preamble of claim 1, and a method according to the dependent patent claims. Background technique [0002] Known from the market is a computing unit, such as a processor, which has one or more processor cores and which can access a working memory. In addition, a computer system having one or more such computing units usually includes a large number of other units that function in conjunction with the computing unit, such as input and output modules ("IO") and the like. At least several of the mentioned elements of the computer system can exchange data with each other via a common, preferably parallel bus. In addition, a method for so-called direct memory access (DMA, English "direct memory access") is also known, whereby data exchange via the common bus can be improved. Summary of the invention [0003] The problem on which the invention is based is solved by a memory direct acc...

Claims

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Application Information

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IPC IPC(8): G06F13/30G06F13/28
CPCG06F13/28G06F13/30
Inventor E.贝克A.奥厄E.施洛特曼
Owner ROBERT BOSCH GMBH