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Power semiconductor device structure and manufacturing method thereof

A technology for power semiconductors and device structures, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., and can solve problems such as the inability to reduce the manufacturing cost of power semiconductor devices.

Inactive Publication Date: 2017-11-28
SYSU CMU SHUNDE INT JOINT RES INST +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention provides a power semiconductor device structure in order to solve the technical defect that the manufacturing cost of the power semiconductor device provided by the above prior art cannot be reduced due to the limitation of the chip area and the size of the single crystal silicon wafer.

Method used

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  • Power semiconductor device structure and manufacturing method thereof
  • Power semiconductor device structure and manufacturing method thereof
  • Power semiconductor device structure and manufacturing method thereof

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Embodiment 1

[0033] figure 1 It is a top view of a power semiconductor device 100 and its corresponding wafer provided in the prior art. As shown in the figure, a large number of identical device chips are arranged at equal intervals on the wafer, including the device chip 100 . There are dicing lanes between the device chips, and different device chips are cut along the dicing lanes during packaging. The size of the dicing lanes is generally tens of microns, which is much smaller than the size of the device chips. Therefore, the number of device chips that can be placed on a wafer depends only on the size of the device chips and the size of the wafer. As mentioned above, the maximum diameter of single crystal silicon wafers currently available in the industry is only 12 inches, while the area of ​​power semiconductor device chips is gradually approaching the theoretical lower limit. Therefore, for the power semiconductor device 100 manufactured based on a single crystal silicon wafer, t...

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PUM

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Abstract

The invention relates to a power semiconductor device structure. The power semiconductor device structure comprises a substrate and a chip array, wherein the chip array is embedded into the substrate, a top public electrode is arranged on upper surfaces of the chip array and the substrate and is used for connecting one end of each chip in the chip array in parallel, and a bottom public electrode is arranged on lower surfaces of the chip array and the substrate and is used for connecting the other ends of chips in the chip array in parallel.

Description

technical field [0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a structure of a power semiconductor device and a manufacturing method thereof. Background technique [0002] Power semiconductor devices are the core of modern power electronic systems, and their cost depends largely on the manufacturing cost of chips. At present, the vast majority of commercialized power semiconductor device chips are manufactured based on single crystal silicon wafers. The more power semiconductor device chips integrated on a wafer, the more power semiconductor device chips that can be processed in batches at one time in the production process, and the lower the cost of each power semiconductor device chip. Based on this industry consensus, reducing the chip area of ​​power semiconductor devices and using large-size wafers are the two most direct means to reduce the manufacturing cost of power semiconductor device chips. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L21/50
CPCH01L21/50H01L25/18H01L2224/02166H01L2224/05H01L2224/06181
Inventor 王凯周贤达单建安
Owner SYSU CMU SHUNDE INT JOINT RES INST