DSP instruction simulation method based on register access conflict detection

A technology of access conflict and simulation method, applied in the direction of concurrent instruction execution, machine execution device, etc., to achieve the effect of ensuring correctness, taking into account efficiency and correctness

Active Publication Date: 2018-01-16
北京轩宇信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0022] Technical problem solving of the present invention: In order to overcome the deficiencies of the prior art, a DSP instruction simulation method based on register access conflict detection is provided to solve the problem of parallelism or delay cycles of instructions

Method used

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  • DSP instruction simulation method based on register access conflict detection
  • DSP instruction simulation method based on register access conflict detection
  • DSP instruction simulation method based on register access conflict detection

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Experimental program
Comparison scheme
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Embodiment

[0054] Below in conjunction with a section of TMS320C6000 DSP instruction code, illustrate the implementation steps of the present invention:

[0055]

[0056]

[0057] In this code, when the instruction is preceded by "||", it means that the address instruction is executed in parallel with the previous instruction. The pipeline characteristics of the ADDDP instruction are shown in the following table:

[0058]

[0059] Among them, E1~E7 are the seven stages of pipeline execution, and each stage occupies one cycle. The E1 stage completes the reading of the low bits of the instruction source operands src1 and src2, and the E2 stage completes the reading of the source operands src1 and src2 high bits. E3~ The E5 stage completes the operation of the ADDDP instruction, the E6 stage writes the low-order dst_l of the operation result into the destination register, and the E7 stage writes the high-order dst_h of the operation result into the destination register.

[0060] In ...

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Abstract

The invention discloses a DSP instruction simulation method based on register access conflict detection. After identifying instructions that do not conform to the sequence characteristic, the simulation of the kind of instructions can be performed through a periodic mode to ensure the correctness of the instruction simulation; for the instructions that conform to the sequence characteristic, the simulation of pipeline characteristics when executing the instructions can be omitted, and the instructions can be quickly simulated in a fast mode by using the existing technology; and the instructions are simulated in different modes respectively by detecting the instruction register access conflict, so that the efficiency and correctness of the instruction simulation can be taken into account.

Description

technical field [0001] The invention relates to a DSP instruction simulation method based on register access conflict detection, aiming at that the TMS320C6000 DSP processor can execute multiple instructions in parallel and the instruction has the characteristics of a delay cycle. Background technique [0002] TMS320C6000 DSP is a high-performance processor of TI Company. This architecture allows up to eight instructions to be executed in parallel, and some instructions have delay cycles. It takes a certain clock cycle to wait from the instruction execution to the execution result. [0003] At present, instruction simulation usually adopts fast instruction simulation technologies such as threading code and dynamic binary translation. When executing, the value of the source operand read is the result after the execution of the previous instruction. [0004] Zhejiang University Patent No. 201310048645.8 discloses a dynamic binary translation method. The specific steps of the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 张西超虞砺琨滕俊元朱倩冀会芳赵欢郑小萌王辉
Owner 北京轩宇信息技术有限公司
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