Method and device for raising word line of SRAM array
A memory array, static random access technology, applied in the semiconductor field, can solve the problems of large layout area and complex control
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[0028] figure 1 The structure of a SRAM cell in the prior art is shown. Such as figure 1 As shown, the SRAM unit includes PMOS transistor ML0, PMOS transistor ML1, NMOS transistor MPG0, NMOS transistor MPG1, NMOS transistor MPD1 and NMOS transistor MPD2. Wherein, when the node N1 is a high voltage, that is, the power supply voltage VDD, and the voltage of the node N0 is a low voltage, that is, the ground voltage VSS, the value stored in the SRAM unit is called a logic 1, otherwise, the value stored in the RAM unit is a logic 0.
[0029] When it is necessary to rewrite the information stored in the SRAM unit, such as rewriting the value stored in it from 1 to 0, the operation to be performed is: Prime Minister, charge the word line WL to a high voltage, that is, the power supply voltage VDD, and charge the bit line of the SRAM unit The voltage of BL is pulled down from the power supply voltage VDD to the ground voltage VSS, and at the same time, the voltage of the bit line BL...
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