Chip architecture reconstruction method and device

Abstract

The invention discloses a chip architecture reconstruction method, which includes the steps of arranging a programmable circuit in an ASIC and setting a configuration file set of configuration files corresponding to different scenes of the programmable circuit; determining a current scene of the ASIC running, and according to the current scene, acquiring a configuration file corresponding to the current scene in the configuration file set; and configuring the programmable circuit by using the determined configuration file corresponding to the current scene. The invention also discloses a chiparchitecture reconstruction device.

Description

technical field [0001] The invention relates to integrated circuit technology, in particular to a chip architecture reconfiguration method and device. Background technique [0002] Once the traditional ASIC (Application Specific Integrated Circuit) chip is physically implemented, its logic function cannot be changed, which makes it often costly to correct its defects, and even requires redesign and production. Although field-programmable gate array (FPGA, Field-Programmable Gate Array) chips can realize configurable functions, and the cost of defect correction is much lower, the cost of chips is high, and special configuration tools are required. At present, in order to reduce product cost, most designers use ASIC as the final product form, and FPGA is used for product prototype verification. [0003] In the design of ASIC architecture, there has always been a trade-off between dedicated acceleration hardware and general-purpose software implementation for specific function...

AI Technical Summary

Problems solved by technology

However, both need to rely on the unique development process of each FPGA, and due to cost and complexity, the corresponding method can only be applied to a specific FPGA design process, and cannot be reused in ASIC design

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