FinFET semiconductor device and manufacturing method thereof

Abstract

The present invention provides an FinFET (Fin Field Effect Transistor) semiconductor device and a manufacturing method thereof. The method comprises: after a first epitaxial layer is formed, a first dielectric layer is deposited on a semiconductor substrate to surround the first epitaxial layer and a second fin; the first dielectric layer in a second region is etched so that the height of the second fin is lower than that of a second sidewall and the height of the first dielectric layer is higher than that of the second fin; second sidewalls of both sides of the second fin are etched, the etching is horizontal etching, etching is performed outwards from the second sidewalls at both sides of the second fin to the second sidewalls with a remaining partial thickness, and in this case, becausethe first dielectric layer is arranged at both sides of the second sidewalls to ensure that the remaining second sidewalls do not collapse due to the reduction in thickness, and then a second epitaxial layer is formed on the second fin and the second sidewalls to prevent the collapse from occurring on the basis of increasing the volume of the epitaxial layer, and finally performances of a semiconductor device are improved.

Description

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AI Technical Summary

Benefits of technology

This patented technology provides an improved way for making transistors without losing their functionality or causing damage during subsequent processing steps such as deposition processes used to create them. It also allows for more precise control over how well these structures work when they're being processed.

Problems solved by technology

This patented technical solution involves creating fins for use within electronic components such as integrated circuits or other types of microelectronics systems. These techniques involve reducing sizes while still allowing more space between different parts of these components without compromising their functionality. To achieve this goal, there needs to have sufficient spacing between certain areas inside each part of the component's circuitry. Additionally, it requires precise placement during manufacturing processes where the material from one area may diffuse into another area causing damage if placed too close together. Existing methods require multiple steps involving etches and then reappropriation of the entire chip surface, leading to increased risk of collapses due to unevenly distributed materials near critical points along the edges of the patterned channels.

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