Time-sharing sampling holding circuit

Abstract

The invention relates to a time-sharing sampling holding circuit comprising an input buffer and a clock processing circuit. The input buffer drives a first sampling holding circuit and a second sampling holding circuit simultaneously and drives a first differential amplifier and a second differential amplifier respectively; the first differential amplifier drives a third sampling holding circuit;and the second differential amplifier drives a fourth sampling holding circuit. The clock processing circuit is used for receiving an external clock signal CLK and then generating clock signals; the clock signals CLK1A and CLK2A drive the first sampling holding circuit and the second sampling holding circuit respectively; the clock signals CLK1B and CLK2B drive the third sampling holding circuit and the fourth sampling holding circuit respectively; and the clock signals CLK1C and CLK2C drive the third sampling holding circuit and the fourth sampling holding circuit respectively. On the basis of the designed clock processing circuit, two sampling channels carry out sampling on analog signals strictly according to an external clock signal frequency, thereby eliminating a phase error and achieving an objective of realizing a high sampling frequency by a circuit with a low sampling frequency.

Description

technical field [0001] The invention belongs to the field of analog / mixed signal integrated circuits, in particular to a time-division sampling and holding circuit. Background technique [0002] The time-sharing sampling circuit uses more than two channels to sample the same analog signal at equal intervals to achieve the purpose of achieving a higher sampling frequency with a circuit with a lower sampling frequency. The time-sharing sampling circuit in the prior art cannot ensure that each sampling channel samples the same analog signal at strict equal intervals, and there is a certain phase error, so the performance is poor. In addition, the signal holding time of the time-division sampling circuit in the prior art is relatively short, which is not conducive to improving system performance. Contents of the invention [0003] In order to overcome the above problems, the present invention provides a time-division sample-and-hold circuit, which eliminates the phase error b...

AI Technical Summary

Problems solved by technology

The time-sharing sampling circuit in the prior art cannot ensure that each sampling channel samples the same analog signal at strict equal intervals, and there is a certain phase error, so the performance is poor

In addition, the signal holding time of the time-division sampling circuit in the prior art is relatively short, which is not conducive to improving system performance

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