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Double Graphical Method

A double patterning and dry etching technology, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve the problems of poor target pattern quality, affecting the performance and yield of semiconductor structures, and achieve improved morphology symmetry , Reduce the effect of etching micro-loading effect and improve the quality

Active Publication Date: 2020-08-07
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Application Information

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Problems solved by technology

[0004] However, in the prior art, the double patterning method is used to etch the substrate, and the quality of the target pattern formed in the substrate after etching is poor, which affects the performance and yield of the formed semiconductor structure

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Embodiment Construction

[0030] It can be seen from the background art that in the prior art, a double patterning method is used to etch the substrate, and the quality of the pattern formed in the etched substrate is poor.

[0031] Figure 1 to Figure 5 It is a schematic cross-sectional structure diagram of a process of forming a semiconductor structure by a double patterning method.

[0032] refer to figure 1 , a substrate 101 is provided, and several discrete core layers 102 are formed on the surface of the substrate 101 .

[0033] And the process of forming the core layer 102 is easy to cause over etching (over etch) to the substrate 101, so that the top surface of the substrate 101 below the core layer 102 is higher than the top surface of the substrate 101 exposed by the core layer 102, and the top surface of the substrate 101 below the core layer 102 The minimum distance between the top of the substrate 101 and the top of the substrate 101 exposed by the core layer 102 is L1.

[0034] refer t...

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Abstract

The invention provides a double patterning method, which comprises the following steps: forming a side wall layer on the top portions and side walls of core layers and on a substrate; forming a sacrificial layer on the side wall layer and filling an area between the adjacent core layers; removing the side wall layer higher than the top portions of the core layers and exposing the top portions of the core layers; carrying out etching to remove a first thickness of the core layers, and etching the top portion of the side wall layer and a first side wall higher than each residual core layer to enable the first side wall higher than the residual core layer to be in an arc shape; removing the sacrificial layer to expose a second side wall of the side wall layer; carrying out back-etching on theside wall layer through an anisotropic etching process, carrying out etching to remove the side wall layer on a part of the substrate, and etching the second side wall and the first side wall of theside wall layer; removing the residual core layers; and with the side wall layer obtained after back-etching as a mask, etching the substrate to form a target pattern. The method improves the qualityof the formed target pattern.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a double patterning method. Background technique [0002] Photolithography technology is the most critical production technology in the semiconductor manufacturing process. With the continuous reduction of semiconductor process nodes, the existing light source lithography technology can no longer meet the needs of semiconductor manufacturing. Extreme ultraviolet lithography (EUV), multi- Beamless maskless technology and nanoimprint technology have become the research hotspots of next-generation lithography candidate technologies. However, the above-mentioned next-generation lithography candidate technologies still have inconveniences and defects, and further improvements are urgently needed. [0003] When Moore's Law continues to extend irreversibly, the double patterning (DP: Double-Patterning) technology has undoubtedly become one of the best choices in the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/033
CPCH01L21/0334
Inventor 张城龙王彦
Owner SEMICON MFG INT (SHANGHAI) CORP
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