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Bootstrap sampling switch circuit, sample and hold circuit and time interleaved ADC

A technology of bootstrap sampling switch and time interleaving, which is applied in electrical components, analog/digital conversion, code conversion, etc., can solve the problems of large output clock jitter, complex structure, large timing deviation of clock signal, etc., to reduce jitter, structure Simple, Timing Mismatch Reduction Effects

Active Publication Date: 2020-11-10
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The technical problem to be solved by the present invention is to overcome the defects of complex voltage bootstrap sampling switch circuit structure, large output clock jitter and large timing deviation between clock signals of each channel in the prior art. , providing a bootstrap sampling switch circuit, a sample-and-hold circuit, and a time-interleaved ADC capable of simplifying additional clock circuits and improving timing matching between channels

Method used

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  • Bootstrap sampling switch circuit, sample and hold circuit and time interleaved ADC
  • Bootstrap sampling switch circuit, sample and hold circuit and time interleaved ADC
  • Bootstrap sampling switch circuit, sample and hold circuit and time interleaved ADC

Examples

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Embodiment 1

[0051] Such as Figure 4 As shown, this embodiment provides a bootstrap sampling switch circuit for time-interleaved ADC, the bootstrap sampling switch circuit includes a charge pump 3, a first capacitor C var , the first NMOS transistor N1, the first PMOS transistor P1, the first clock input terminal 4, the gate input terminal 5, the clock output terminal 6, the duty ratio adjustment circuit 1, the synchronization circuit 2, and the second NMOS transistor R var and the third NMOS tube M pd .

[0052] The strobe input terminal 5 is used to access the sampling selection signal sel of the i-th sub-ADC channel of the time-interleaved ADC , the first clock input terminal 4 is used to access the system clock ck_adc of the time-interleaved ADC, and the clock output terminal 6 is used to output the sampling clock signal cksp_bst , the sampling clock signal cksp_bst It is used to control the sampling switch of the sampling and holding circuit of the ith sub-ADC of the time-interle...

Embodiment 2

[0069] The difference between this embodiment and Implementation 1 is that the first capacitor C var use as Figure 9 The circuit shown is implemented. and Image 6 the difference is, Figure 9 The first capacitor C is controlled by controlling the reset level of the capacitor during the reset phase, that is, when the sel_int_n signal is high. var The equivalent capacitance value size. If the array capacitor C1 is selected, that is, the corresponding second control signal is high, the lower plate of the capacitor will be connected to the ground when it is reset, and the upper plate will be charged to the bias voltage pwr, so the array capacitor C1 The voltage is pwr. And if the array capacitor C1 is not selected, the lower plate is connected to pwr when reset, and the upper plate is also pwr, so the voltage of this capacitor is 0, similar to the fact that the array capacitor C1 does not exist.

Embodiment 3

[0071] Such as Figure 10 As shown, this embodiment provides a sample-and-hold circuit for a sub-ADC in a time-interleaved ADC, and the sample-and-hold circuit includes a sampling switch S 3 And the bootstrap sampling switch circuit described in Embodiment 1, the sampling clock signal cksp_bst output by the clock output terminal used to control the sampling switch S 3 .

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Abstract

The invention discloses a bootstrapped sample switch circuit, a sample hold circuit and a time-interleaved ADC. The bootstrapped sample switch circuit comprises a charge pump, a first capacitor, a first NMOS transistor, a first PMOS transistor, a first clock input end, a gating input end, a clock output end, a duty cycle adjustment circuit, a synchronous circuit, a second NMOS transistor and a third NMOS transistor. The gating input end is used for access of sample selection signals of sub-ADC channels of the time-interleaved ADC. The first clock input end is used for access of a system clock.The clock output end is used for outputting a sample clock signal. The sample clock signal is used for controlling sample switches of the sample hold circuits of sub-ADCs. According to the bootstrapped sample switch circuit, the sample hold circuit and the time-interleaved ADC, combination logic is carried out through utilization of the system clock of the time-interleaved ADC and the sample selection signals of the sub-ADC channels generated by a digital platform, thereby generating the sample clock signals, the jitter is greatly reduced, an additional clock circuit is simplified, and the time sequence matching between channels is improved.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a bootstrap sampling switch circuit, a sample-and-hold circuit and a time-interleaved ADC (analog-to-digital converter) used in an analog-to-digital converter circuit. Background technique [0002] Analog-to-digital converters are used to convert analog signals into digital signals, and are widely used in various data acquisition and communication systems. The sampling rate of the ADC directly determines the signal bandwidth that can be processed, and the accuracy of the ADC (such as the signal-to-noise ratio SNR, spurious-free dynamic range SFDR, etc.) determines the dynamic range of the entire system. ADC has a variety of architectures, such as pipelined ADC, successive approximation (SAR ADC), flash ADC, and interleaved ADC. In these architectures, the time-interleaved ADC is composed of multiple low-speed (relatively speaking) sub-ADCs for time interleaving, so it can grea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/12
CPCH03M1/123H03M1/1255
Inventor 张辉富浩宇高远王海军陈正李琪林李丹
Owner SHANGHAI BEILING
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