Clock data recovery circuit and implementation method

Abstract

The invention relates to a clock data recovery circuit and an implementing method. The clock data recovery circuit is used through the steps of conducting continuous sampling through a resampling circuit to obtain a resampling data stream, conducting filtering treatment on the resampling data stream through a filtering circuit to obtain a filtering data stream, conducting extract sampling treatment on the filtering data stream through an extract sampling circuit to obtain an extract sampling data stream, conducting asynchronizing treatment on the extract sampling data through an asynchronizingFIFO circuit to obtain an asynchronizing data stream, and conducting cache arrangement on the asynchronizing data stream through an elastic cache circuit to obtain a recovered output data stream. Theclock data recovery circuit has the advantages of being good in reliability, good in shake resistance and high in initial frequency offset tolerance, and a high-speed serial transceiver can be easilyobtained.

Description

technical field [0001] The invention relates to the field of data communication, and is applicable to the design and realization of a high-speed interface circuit clock data recovery circuit. Background technique [0002] Clock and Data Recovery (CDR) circuits are an important part of high-speed data transmission systems and are widely used in high-speed serial transceivers. [0003] Traditional CDR circuits can basically be divided into two categories: [0004] The first type is phase tracking CDR (phase tracking CDR). The advantage of this kind of circuit is that the structure is simple, and more importantly, the sampling clock can be adjusted in real time, so it has a high tolerance for initial frequency deviation, but it is necessary to track and lock the phase of the received data in real time and quickly. The requirements are relatively high, which is difficult to achieve in high-frequency design, and the anti-jitter ability is relatively poor. [0005] The second i...

AI Technical Summary

Problems solved by technology

However, this circuit architecture is relatively complex, and the power consumption and delay are relatively large.

[0006] It can be seen that the general CDR circuit cannot guarantee the anti-jitter capability of the circuit and have a high tolerance for initial frequency deviation

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