Low-power dissipation parallel multiplier

Abstract

The invention provides a low-power dissipation parallel multiplier. The low-power dissipation parallel multiplier includes a partial product generation module, a partial product compression module, and a carry-skip adder. The partial product generation module includes a Booth encoding circuit and a Booth decoding circuit; the Booth encoding circuit encodes a place value adjacent to a first multiplicator into a target parameter; the Booth decoding circuit decodes a place value of a second multiplicator and the target parameter into a partial product; and the partial product generation module can reduce the number of the partial products by half, the area of the multiplier circuit is greatly saved, and the operation speed of the multiplier circuit is improved. The partial product compressionmodule includes a one-bit full adder and a summing circuit; the one-bit full adder outputs a reversed value of a carry bit according to the partial products; the summing circuit adds the partial products to generate two target partial products with different weights and outputs the target partial products to a subordinate compression module, and in this way, the compression speed of the partial products is greatly improved. The carry-skip adder includes a plurality of CSA modules and is used for acquiring a target product.

Description

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AI Technical Summary

Benefits of technology

This technology provides better performance than previous designs but at least partially overcomes their limitations such as requiring more space on the device or slowed down calculations due to increased processing time caused by partial products being added during computation. It achieves this through reducing the amount of memory needed per unit length (per byte) used compared to traditional methods like adding extra bits). Additionally, there are also improvements that can be made without affecting certain aspects of the algorithm's behavior. Overall, these techniques improve efficiency and reduce size requirements within modern electronic devices.

Problems solved by technology

This patented technology describes a method called multi-bit multiplication which can achieve both high computation speeds with small circuits while maintaining simplicity compared to traditional methods like Montgomery techniques or other conventional ways of calculating numbers quickly by combining multiple smaller parts together.

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