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Single event hardened clock control circuit and control method in a programmable configuration logic block

A single-event reinforcement and configuration logic technology, applied in the direction of logic circuits with logic functions, etc., can solve the problems of limited programmable anti-single-event overturn capability, user function interruption, user storage data errors and other problems, to improve the anti-single event. The effect of flipping ability, meeting timing requirements, and reducing the probability of decoding errors

Active Publication Date: 2022-01-11
BEIJING MXTRONICS CORP +1
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the influence of the space single event effect, the data in the programmable user register will undergo a single event flip, resulting in an error in the user's stored data. If a single event flip occurs, the user function will be interrupted
The clock control circuit in the traditional programmable configuration logic block controls clock decoding and shifting operations by generating pulses to repeatedly read and write memory cells, which has flexible programmable characteristics and anti-single event flipping capabilities for programmable logic devices limited

Method used

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  • Single event hardened clock control circuit and control method in a programmable configuration logic block
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  • Single event hardened clock control circuit and control method in a programmable configuration logic block

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Embodiment Construction

[0045] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0046] A single-particle reinforced clock control circuit and control method in a programmable configuration logic block of the present invention abandons the traditional clock control circuit, adopts timing and LAT structures to realize the latching and decoding of row, column and data signals, and realizes Synchronize the enable signal with the clock signal to generate a shifted overlapping clock to control the shifting of data; on this basis, the reinforced SRAM and the reinforced RS flip-flop design are used to realize the anti-single event hardening function of the user register, which improves the clock control circuit ability to resist single-event upsets. The single event reinforcement index in the single event hardened clock control circuit of the present invention is 3 orders of magnitude higher than that of the traditional ...

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Abstract

A single event hardened clock control circuit and control method in a programmable configuration logic block, abandoning the traditional clock control circuit, using timing and LAT structure to realize the latching and decoding of row, column and data signals, and realizing the use of The energy signal is synchronized with the clock signal to generate a shifted overlapping clock to control the shifting of data; on this basis, the reinforced SRAM and the reinforced RS flip-flop are designed to realize the anti-single event hardening function of the user register, which improves the anti-single event hardening function of the clock control circuit. The ability to flip over a single instance. The single event reinforcement index in the single event hardened clock control circuit of the present invention is 3 orders of magnitude higher than that of the traditional register, so that users have higher flexibility, better timing performance and extremely high resistance to single event when using programmable user registers Reinforcement indicators.

Description

technical field [0001] The present invention relates to a single event hardened clock control circuit and control method in a programmable configuration logic block, in particular to a clock control circuit and control method in a programmable configuration logic block optimized for the application requirements of programmable logic devices. The method belongs to the field of integrated circuits. Background technique [0002] Programmable logic devices have the advantages of high flexibility, low cost, and short cycle time. They can greatly shorten the product development cycle and minimize risks. They have become core components in the integrated circuit industry. Among them, the clock control read-write circuit in the programmable configuration logic block is the core circuit in the programmable logic device to realize the user's logic function, and can be programmed to realize various sequential functions according to the user's needs. Due to the influence of the space s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/20
CPCH03K19/20
Inventor 陈雷郭琨文治平倪劼孙华波王文锋孙健爽钱涛涛刘亚泽
Owner BEIJING MXTRONICS CORP
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