Dual programmable subtraction frequency divider

A frequency divider and subtraction technology, applied in the field of microelectronics, can solve the problems of increased circuit complexity and power consumption

Inactive Publication Date: 2013-03-27
HANGZHOU DIANZI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This structure requires multiple flip-flops to achieve the purpose of dual programming, and the complexity and power consumption of the circuit are greatly increased.

Method used

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  • Dual programmable subtraction frequency divider
  • Dual programmable subtraction frequency divider
  • Dual programmable subtraction frequency divider

Examples

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Embodiment Construction

[0023] Such as figure 1 As shown, a dual-programmable subtraction divider includes a preset minus-1 counter 2, a logic comparator 3 and two registers 1 and 4.

[0024] Such as figure 2 As shown, the preset decrement counter 2 includes five-stage presettable T flip-flops T-1~5 and three-stage AND gates AND-1~3.

[0025] Presettable T flip-flops T-1~5 include data input port T, clock input port CLK, enable signal input port SE, preset number input port SD, non-inverting output port Q, and inverting output port QN; When the input port SE is valid, under the action of the clock signal, the signal of the preset number input port SD is directly output to the same-phase output port Q; when the enable signal input port SE is invalid, under the action of the clock signal, the signal of the data input port T is directly output Output to non-inverting output port Q.

[0026] The enable signal input ports SE of the five-stage presettable T flip-flops T-1~5 are connected as the enable ...

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PUM

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Abstract

The invention relates to a dual programmable subtraction frequency divider. The existing frequency divider circuit has great complexity and high power consumption. The dual programmable subtraction frequency divider comprises a presettable 1 subtracted counter, a logic comparator and two registers. The presettable 1 subtracted counter comprises N (N is not less than 3) stages of presettable T triggers and M (M=N-2) stages of AND gates; the logic comparator comprises N stages of XOR gates and one NOR gate; an input end of the first register is connected with a first external preset number, and the input end of the second register is connected with a second external preset number; and an output port of the logic comparator is used as the output end of the dual programmable subtraction frequency divider. The frequency dividing ratio of the dual programmable subtraction frequency divider is controlled by two input frequency dividing preset numbers, circuits are implemented simply, and the programmable flexibility of the frequency dividing ratio is high.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to a double programmable subtraction frequency divider. Background technique [0002] A frequency synthesizer is a component that realizes frequency conversion and channel selection in a wireless receiver, and a multimode frequency divider is a key module in a frequency synthesizer. With the continuous development of communication technology, multi-mode and multi-frequency has become the development trend of receivers. To realize a multi-mode multi-frequency receiver, the multi-mode frequency divider in the phase-locked loop must be flexible and programmable. On the other hand, in some special applications, such as fractional frequency division phase-locked loops, the frequency division ratio of the multimode frequency divider is controlled by two signals, one signal controls the integer frequency division, and the other signal is the sigma-delta modulator The transient outp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/08H03L7/18
Inventor 高海军孙玲玲
Owner HANGZHOU DIANZI UNIV
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