Encapsulation structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor/solid-state device testing/measurement, etc., can solve the problems of increasing manufacturing cost, scrapping, waste of raw materials and components, etc.
Active Publication Date: 2021-03-09
INNOLUX CORP
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- Description
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Problems solved by technology
However, if a defect occurs in the subsequent manufacturing process, the packaged qualified electronic components must be scrapped together with the entire package body, resulting in waste of raw materials and components, and increasing manufacturing costs. Therefore, the traditional electronic component packaging method still needs to be further improved
Method used
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no. 1 example
[0079] After the redistribution layer RDL is manufactured and before the electronic components are bonded, the first stage of testing can be optionally performed to test the redistribution layer RDL. Wherein, the test machine 300 respectively contacts and electrically connects the bonding electrodes 2141' via a set of probes 310, and contacts and electrically connects the testing electrodes 2221 via another set of probes 312, so as to perform a short circuit test and an open circuit test. According to the requirements in different manufacturing processes and the design of the test machine 300 , the test machine 300 can test a single package structure unit UT, or test a plurality of package structure unit UTs at the same time. It should be noted that, in this embodiment, each package structure unit UT has a second wiring region R2, and the second wiring region R2 is provided with a test pad 220 and a test lead 222 including a test electrode 2221, so a tester can be used to The ...
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Abstract
The invention provides a packaging structure, which includes a redistribution layer, a welding layer and an electronic component. The rewiring layer has a first wiring region and an adjacent second wiring region, a bonding electrode and a testing electrode are arranged on the first surface of the rewiring layer, wherein the bonding electrode overlaps with the first wiring region, and the testing electrode overlaps with the second wiring region. The wiring area overlaps, and the welding layer is located on the second surface of the redistribution layer, and has a plurality of conductive pads separated from each other, and each conductive pad is electrically connected to one of the bonding electrode and the testing electrode. The redistribution layer further includes a plurality of dielectric layers and a plurality of patterned conductive layers, the dielectric layer has a plurality of through holes, and part of the patterned conductive layers are located in the through holes. The bonding electrodes are electrically connected to the corresponding conductive pads by means of the corresponding patterned conductive layers to form redistribution wires, the test electrodes are electrically connected to the corresponding conductive pads by means of the corresponding patterned conductive layers to form test wires, and the electronic components are electrically connected to the bonding pads. electrode.
Description
technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof, in particular to a panel-level packaging structure and a manufacturing method thereof. Background technique [0002] In the packaging technology of electronic components, the fan-out wafer level package (FOWLP) structure is to manufacture electronic components on a wafer for packaging and dicing. However, since the diameter of today's common large-size wafers is only about 300 millimeters (mm), the number of electronic components that can be packaged on the wafer at the same time is limited, and the industry still needs to actively develop technologies to replace wafer-level packaging. [0003] Moreover, in the manufacturing process of the traditional fan-out packaging structure, a relatively mature technology is to firstly arrange electronic components on a carrier such as a wafer, and then arrange a redistribution layer on the electronic components. Among them, in ord...
Claims
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IPC IPC(8): H01L21/66H01L21/60H01L23/485
CPCH01L22/14H01L22/32H01L24/03H01L24/05H01L2224/0231H01L2224/02331H01L2224/02333H01L2224/16225H01L2224/81H01L2224/97H01L2924/15311H01L2924/18161
Inventor 周学轩范家杰王程麒王冠人
Owner INNOLUX CORP