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Sampling network circuit and sampling chip

A network circuit and sampling capacitor technology, applied in the field of electronics, can solve the problems such as the influence of the load of the linearity pre-stage circuit, and achieve the effect of small influence of sampling linearity, simple circuit structure, and reduced load influence.

Active Publication Date: 2021-10-29
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to overcome the fact that the input switching tube has a great influence on the linearity of the sampling network and the load of the previous stage circuit due to the substrate bias mode of the input switching tube in the sampling network in the prior art defect, a sampling network circuit and a sampling chip are provided

Method used

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  • Sampling network circuit and sampling chip
  • Sampling network circuit and sampling chip
  • Sampling network circuit and sampling chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] Such as figure 1 As shown, the sampling network circuit involved in this embodiment includes an input switch M1 and a first switch ckh1. At this time, the substrate (bulk) of the input switch M1 receives the first fixed voltage Vbuk through the first switch ckh1, that is, the bulk is drawn out The terminal Vb is connected to the first fixed voltage Vbuk; in the holding phase, the first switch ckh1 is in the on state, so that the first fixed voltage Vbuk is used as the bias voltage of the bulk; in the sampling phase, the first switch ckh1 is in the off state, so that the The bulk is floating.

[0032] In a specific implementation, a bootstrap circuit may be used to drive the gate of the input switch M1 to keep the gate-source voltage constant. Specifically, the sampling network circuit also includes a grid voltage bootstrap circuit 1, the input terminal of the grid voltage bootstrap circuit 1 is connected to the source of the input switch M1 (Vs in the figure) to receiv...

Embodiment 2

[0043] Such as image 3 As shown, the sampling network circuit involved in this embodiment is basically the same as that of Embodiment 1, the difference is that the DNW of the input switch M1 also adopts a dynamic bias method. Specifically, the sampling network circuit also includes a second switch ckh2, and the deep n well (Vn-well in the figure) receives the second fixed voltage Vnwell through the second switch ckh2, that is, the DNW lead-out terminal Vn-well passes through the second switch ckh2 is connected to the second fixed voltage Vnwell; in the holding phase, the second switch ckh2 is in the open state, so that the second fixed voltage Vnwell is used as the bias voltage of DNW; in the sampling phase, the second switch ckh2 is in the open state, so that the DNW Floating.

[0044] In this embodiment, parasitic capacitance is also used to store charges to dynamically bias the DNW of the input switching tube M1, that is, when the second switch ckh2 is in the ON state, th...

Embodiment 3

[0052] This embodiment relates to a sampling chip. The sampling chip is based on the sampling network circuit described in Embodiment 1 or Embodiment 2 above. In this way, the sampling network circuit is integrated into the sampling chip, which is convenient for application.

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Abstract

The invention discloses a sampling network circuit and a sampling chip, wherein the sampling network circuit includes an input switch tube, the sampling network circuit further includes a first switch, and the substrate of the input switch tube receives A first fixed voltage; in the holding phase, the first switch is in the on state; in the sampling phase, the first switch is in the off state. The present invention utilizes the parasitic capacitance characteristics of the first switch and the input switch tube to dynamically bias the substrate of the input switch tube, and significantly reduces the impact of the input switch tube on the front stage while maintaining a simple circuit structure and high linearity. circuit load effects.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a sampling network circuit and a sampling chip. Background technique [0002] The traditional sampling network circuit is generally composed of an input switching tube, a sampling capacitor and a sampling switch. The input switching tube generally adopts an NMOS tube, so that the input signal Vin is input to the source of the NMOS tube, so that the bulk of the NMOS tube can generally be input by Signal drive (such as direct drive or buffer drive) or fixed bias drive, when the bulk is directly driven by the input signal, due to the internal parasitic capacitance characteristics of the NMOS tube, the NMOS tube will constitute a large load on the previous circuit, which will not only increase The power consumption of the previous stage is not conducive to improving the signal bandwidth; when the bulk is driven by the input signal through the buffer, in low-voltage and low-power ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/12H03M1/46
CPCH03M1/1245H03M1/466
Inventor 李丹张辉王海军富浩宇陈正李琪林高远魏亮朱腓力
Owner SHANGHAI BEILING