Supercharge Your Innovation With Domain-Expert AI Agents!

Pipeline multiplexer loop architecture for decision feedback equalizer circuits

A decision feedback equalization, multiplexer technology, applied in instruments, electrical components, static memory, etc., can solve the problems of limited speed and large final size of parallel architectures

Active Publication Date: 2018-07-17
HUAWEI TECH CO LTD
View PDF6 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the number of stages L increases, the final size of the parallel architecture may be larger and may limit the speed

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Pipeline multiplexer loop architecture for decision feedback equalizer circuits
  • Pipeline multiplexer loop architecture for decision feedback equalizer circuits
  • Pipeline multiplexer loop architecture for decision feedback equalizer circuits

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] The present invention generally relates to circuits, methods and apparatus for decision feedback equalization. In some examples, embodiments of the invention may result in smaller, faster and / or simpler multiplexer ring architectures. In some examples, application of the multiplexer ring architecture described herein may allow for greater parallelization, higher clock speeds, and / or higher throughput in parallel processing decision feedback circuits.

[0022] Figure 1A An example circuit 100 is shown showing a series-connected single-tap (1-tap) decision feedback equalizer (DFE) filter with a feedback loop, where the output X[n] is based on the previous output value X[n- 1] multiplied by the quantized value of the input Y[n] adjusted by the tap coefficient C. In this example, the quantizer 110 (also sometimes referred to as a slicer) is a 2-stage quantizer.

[0023] Figure 1B An example circuit 101 is shown where Figure 1A The circuit 100 adjusts the input value b...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention discloses circuits (300, 400), devices, methods for decision feedback equalization. A decision feedback circuit (300) can include a plurality of decision feedback equalizer (DFE)branches, each DFE branch including: a pre-computation stage (305) configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous outputfor the same DFE branch; and a decision feedback stage (306) comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputsfrom other DFE branches. For at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage (306) of at least thefirst DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches.

Description

[0001] Related Applications Cross Application [0002] This application for patent claims priority to prior application of U.S. Patent Application No. 14 / 840,500, filed August 31, 2015, entitled "Pipelined Multiplexer Ring Architecture for Decision Feedback Equalization Circuits," The content of this prior application is incorporated herein by reference. technical field [0003] The present invention generally relates to the field of electronic signal processing circuits, and more particularly, to decision feedback circuits. Background technique [0004] Equalization techniques can be used to improve signal quality or correct digital signals. In digital feedback loops, loop unrolling is a technique that precomputes all possible combinations of filter multiplications and additions before selecting an output based on previous outputs. For parallel circuits, the output of each branch must be valid for a single clock cycle, so the speed of the unrolled loop may be limited as t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G11C7/02H04L25/03
CPCH04L25/03146H04L25/03057
Inventor 洪霍
Owner HUAWEI TECH CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com