Method for converting long-width operand instructions to short-width operand instructions

Abstract

The invention provides a method for converting a long bit wide operand instruction into a short bit wide operand instruction. The long bit wide operand instruction includes two or more fields of two or more registers, and each of the registers can store one long bit wide source operand. The method includes the steps that a first field is selected from the fields; one register which is appointed bythe first field to be used for storing two short bit wide source operands, wherein the two short bit wide source operands are stored at the high half part and the low half part of the register; the bit wide of the short bit wide source operands is appointed in the instruction, and is smaller than that of the long bit wide source operands. The invention further provides a method for executing theshort bit wide operands.

Description

Technical field [0001] The present invention relates to the technical field of microprocessor architecture. More specifically, the present invention relates to a method for converting an original long-bit-width operand instruction into a short-bit-width operand instruction and a method for executing the short-bit-width operand instruction. Background technique [0002] For the current mainstream microprocessors, the types and numbers of registers visible to the programmer are generally specified in the architecture manual. For example, in the Power instruction architecture, the general-purpose registers visible to programmers include: 32 64-bit fixed-point registers, 32 64-bit floating-point registers, and 32 128-bit vector registers. Regarding the super-scalar architecture design, at the implementation level of the microarchitecture, register renaming technology is usually used. For example, in the Power example, there are dedicated fixed-point register renaming components and r...

AI Technical Summary

Problems solved by technology

In most cases, whether it is a commercial processor architecture manual or an actual implementation, operations are performed on operands of full register width, even though in many cases the number of source operands participating in the operation in the instruction is less than 64 bit (maybe only 32-bit or 16-bit width), the high-order field of the register will also be used as a sign bit, which leads to a large number of useless sign bits in the register

Some processors provide a scheme for register sharing (that is, writing multiple results into the same register) for calculation results, but this scheme needs to predict the bit width of instruction operation results, resulting in the need to add additional predictive component

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