A circuit and method for reducing analog voltage measurement error
A technology of simulating voltage and measurement error, applied in the field of voltage measurement, can solve problems such as limited strength, voltage deviation from actual voltage, and contact resistance of needle sticking, so as to reduce adverse effects, ensure accuracy, and reduce errors.
Active Publication Date: 2020-06-16
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0003] The current analog voltage measurement, especially the CP (Chip Probe, in the test) test, generally uses a needle card (a bare chip test fixture with many capillary needles) to test, because the probe used for electrical contact Very thin, the diameter of the needle tip is about 10-100um, and the strength is limited. The force on the pad should not be too large, so there will inevitably be contact resistance when the needle is inserted. When the power consumption is large, it will affect the zero potential of the chip to the ground, resulting in measurement The output voltage deviates from the actual voltage, and the probe still has capacitive or inductive effects at high frequencies
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[0020] The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0021] figure 1 It is a circuit structure diagram of a circuit for reducing analog voltage measurement errors in the present invention. Such as figure 1 Shown, the present invention reduces a kind of circuit of analog voltage measurement error, comprises first impedance network 10, second impedance network 20, the 3rd impedance network 30, the 4th impedance network 40, untested chip (Die) ...
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The invention discloses a circuit and a method for reducing the analog voltage measurement error. The circuit comprises a first impedance network, a second impedance network, a third impedance network, a fourth impedance network and a to-be-measured bare chip. A certain digital input pin IN of the to-be-measured bare chip is connected with an ILOAD load current source equivalent to the working current Icc of the to-be-measured bare chip or equivalent in amplitude with the working current Icc of the to-be-measured bare chip. Through the invention, the adverse effect caused by the contact resistance of a probe can be reduced, and the accuracy of the analog voltage measurement is guaranteed.
Description
technical field [0001] The invention relates to the technical field of voltage measurement, in particular to a circuit and method for reducing analog voltage measurement errors. Background technique [0002] Generally speaking, when performing high-precision analog voltage measurement, it is necessary to ensure that the ground potential is 0 in order to measure an accurate value. [0003] The current analog voltage measurement, especially the CP (Chip Probe, in the test) test, generally uses a needle card (a bare chip test fixture with many capillary needles) to test, because the probe used for electrical contact Very thin, the diameter of the needle tip is about 10-100um, and the strength is limited. The force on the pad should not be too large, so there will inevitably be contact resistance when the needle is inserted. When the power consumption is large, it will affect the zero potential of the chip to the ground, resulting in measurement The output voltage deviates from...
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IPC IPC(8): G01R19/00
CPCG01R19/0084
Inventor 索鑫
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP