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Method for forming vias in wafer level packaging

A technology of wafer-level packaging and device wafers, which is applied to semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problem of large etching aperture and achieve the effect of easy filling

Active Publication Date: 2020-12-18
NINGBO SEMICON INT CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Aiming at the deficiencies of the prior art, the present invention proposes a method for forming through holes in wafer-level packaging and a method for manufacturing semiconductor devices, which can avoid organic film layer etching when etching deep holes in organic film and inorganic composite film layers. The problem of large corrosion hole diameter

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  • Method for forming vias in wafer level packaging
  • Method for forming vias in wafer level packaging
  • Method for forming vias in wafer level packaging

Examples

Experimental program
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Effect test

Embodiment 1

[0053] Figure 3A ~ Figure 3F A schematic cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for forming a via hole in a wafer level package according to an embodiment of the present invention is shown.

[0054] Combine below Figure 3A ~ Figure 3F The implementation process of the method for forming a through hole in a wafer level package according to an embodiment of the present invention is exemplarily described.

[0055] First, as Figure 3A As shown, a device wafer 300 formed with a first chip 301 is provided, and a plurality of second chips 501 are attached to the front or back of the device wafer 300 through a chip attach film 302 .

[0056] The device wafer 300 is a wafer for completing device fabrication, which can be fabricated according to a corresponding layout design using an integrated circuit fabrication technology. devices, and structures such as an interconnect layer composed of a dielectric layer an...

Embodiment 2

[0083] Combine below Figure 4A ~ Figure 4F An exemplary description is given to the implementation process of the method for forming via holes in wafer level packaging according to another embodiment of the present invention.

[0084] First, if Figure 4A As shown, a device wafer 400 formed with a first chip 401 is provided, and a plurality of second chips 501 are pasted on the front or back of the device wafer 400 through a chip connection film 402 .

[0085] The device wafer 400 is similar to the device wafer 300 , and the description of the wafer for completing the device fabrication is omitted here. Both the first chip 401 and the second chip 501 may be various types of chips. The difference from Embodiment 1 is that in this embodiment, the second chip 501 and the first chip 401 are arranged staggered from each other.

[0086] Similarly, the front side of the device wafer 400 refers to the side on which the first chip 401 is formed on the device wafer 400, and the back...

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Abstract

The invention provides a method for forming a through hole in wafer-level package. The method comprises the following steps: providing a device wafer formed with a first chip, wherein multiple secondchips are adhered on the front or back of the device wafer through a chip connecting film; forming a mask layer with an opening on another surface opposite to one surface of the device wafer adhered with multiple second chips; respectively executing etching for more than twice on the device wafer and the chip connecting film by taking the mask layer as the mask, thereby forming the through hole penetrating the device wafer and the chip connecting film, wherein the etching for etching the device wafer is performed before performing the step of etching the chip connecting film every time, and etching through the chip connecting film only at the moment of performing the last etching on the chip connecting film. Through the method for forming the through hole in the wafer-level package, the problem that etching pore is large when the chip connecting film is manufactured through the through hole can be avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming through holes in wafer-level packaging. Background technique [0002] System in Package (SiP, System in Package) is to combine multiple active components with different functions, passive components, micro-electromechanical systems (MEMS) and other components such as optical components into one unit to form a single unit that can provide multiple functions. A system or subsystem that allows heterogeneous IC (Integrated Circuit) integration is the best way to package integration. Compared with SOC (system on chip, system on chip), SiP integration has the advantages of relatively simple, shorter design cycle and market cycle, and lower cost, and SiP can realize more complex systems. Compared with traditional SiP, wafer level system package (waferlevel system in package, WLPSIP) is the process of completing package integration on the wafer, which has the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/48
CPCH01L21/76898H01L23/481
Inventor 刘孟彬
Owner NINGBO SEMICON INT CORP