A method for detecting the connectivity of dielectric layer holes on a wafer

Abstract

The invention provides a method for detecting the connectivity of ducts of a dielectric layer on a wafer. The method comprises the steps: providing the wafer, and sequentially covering the surface ofthe wafer through the dielectric layer and a medium blocking layer, wherein the dielectric layer is provided with a plurality of metal interconnection structures in advance, two sides of the dielectric layer are provided with a sealing structure, and the sealing structure employs the same manufacturing technology as the metal interconnection structures, and also comprises a lead structure. The method also comprises the following steps: making cutting lines in a direction parallel to the length and width directions of the metal interconnection structures, cutting the wafer, and obtaining a plurality of groups of to-be-detected samples; enabling a conductive structure to be connected with a pedestal through an aluminum wire; carrying out the resistance testing of each to-be-detected sample through a testing platform under a predetermined condition; collecting the resistance data, and drawing a resistance-time relation curve; and calculating a duct connectivity parameter. The beneficial effects are that the method can achieve the convenient in-situ measurement of the connectivity of the ducts of the porous dielectric layer of a rear end, completes the quantitative evaluation, and provides the basis for the evaluation and improvement of the technology.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for detecting the connectivity of holes in a dielectric layer on a wafer. Background technique [0002] With the continuous miniaturization of components and the continuous scale-up of integrated circuits, the RC delay at the back end has become an important factor affecting the signal processing rate of integrated circuits. RC delay is the delay generated between the resistance of the wires on the integrated circuit and the parasitic capacitance between the layers. In order to reduce the RC delay of the back-end interconnection, in the current high-tech node (such as 28nm and 55nm) process, the dielectric constant of the filling medium is often reduced by increasing the porosity of the filling medium between the metal interconnection lines, thereby Reduce RC delay. [0003] However, increasing the porosity of the medium will have some adverse effects on the ...

AI Technical Summary

Problems solved by technology

Since the propagation of light, X-rays or neutrons in the medium will be interfered by a large number of metal interconnection lines, it is also impossible to accurately calculate its pore structure

[0009] The positronium annihilation method characterizes the pore structure by measuring the annihilation lifetime spectrum of positronium. Since positronium is sensitive to defects of various sizes (vacancies, holes, impurities, etc.), it is also easy to detect holes. Disturbed by metal lines in the dielectric and defects at the metal / dielectric interface, leading to underestimation of its pore connectivity

[0010] In addition, the existing methods are all complicated to operate, and all require sophisticated and expensive instruments, and the cost is relatively high.

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