Semiconductor structure with gate height scaling

Abstract

The invention relates to a semiconductor structure with gate height scaling. The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture. The method includes: forming at least one dummy gate structure with hardmask material; forming a plurality of materials over source and drain regions on sides of the at least one dummy gate structure; removing upper materials of the hardmask material such that a first material of the hardmask material remains on the dummy gate structure and in combination with a blocking material of the plurality of materials maintains a uniform gate height; forming a replacement gate structure by removing remaining material of the dummy gate structure to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.

Description

technical field [0001] The present disclosure relates to semiconductor structures, and more particularly, to semiconductor gate structures with gate height scaling and methods of fabrication. Background technique [0002] Transistor scaling has been achieved through pitch scaling and other factors. For example, current scaling elements focus on items that affect the transistor's foot-print, such as gate pitch, channel length, spacer thickness, contact critical dimension (CD), metal pitch, and Fin grid pitch for advanced technology. However, as transistors shrink further to gate pitches of about 50nm and beyond, different factors (besides footprint) start to play a more important role. For example, initial gate heights of 50nm and above start to play a significant role in scaling. [0003] Due to the recorded process, the initial gate height needs to be very high, eg 85nm and higher. This is mainly due to oxide material loss during the dummy gate removal and gate pre-clea...

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Problems solved by technology

[0004] However, due to the recorded process, a large budget (thick layer) of the ILD is required for initial gate height

Furthermore, in subsequent processes, such as a self-aligned contact etch process, the oxide ILD needs to be etched with a chemistry that is selective to the gate cap material (e.g., SiN material); however, oxide etch for nitride Selectivity is not very good, which leads to additional oxide loss

Therefore, due to this material loss, the initial height of the replacement gate structure needs to be very high, which can lead to bowing and other manufacturing issues

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