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A three-dimensional stacked flash memory structure and its preparation method

A three-dimensional stacking and flash memory technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as increased capture charge ratio, program interference, silicon substrate leakage, etc., to minimize layout area, improve storage performance, and expand length Effect

Active Publication Date: 2021-03-19
DOSILICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] On the other hand, with the continuous integration of Nand flash memory chips, the unit transistors MC~MC of the existing Nand flash memory storage devices that form transmission channels on the plane The channel length will be shortened
Subsequently, the existing Nand flash memory chip will have short channel effect, leakage current of silicon substrate, gate-induced drain leakage current, reduction of potential barrier introduced by drain terminal, program interference, and increase of lost captured charge ratio.
At the same time, due to the adjacent cell transistors MC~MC Interference between, resulting in threshold voltage changes and other issues

Method used

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  • A three-dimensional stacked flash memory structure and its preparation method
  • A three-dimensional stacked flash memory structure and its preparation method
  • A three-dimensional stacked flash memory structure and its preparation method

Examples

Experimental program
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Embodiment 1

[0046] In a preferred embodiment, as figure 2 As shown, a three-dimensional stacked flash memory structure is proposed, which may include:

[0047] The substrate 100 is made of semiconductor material;

[0048] The supporting board FBAR is formed on the upper surface of the substrate 100 and is made of semiconductor material;

[0049] The first side structure PaTa is formed on the first side of the support plate FBAR and is at the same height as the support plate FBAR;

[0050] The second side structure PaTb is formed on the second side of the support plate FBAR facing away from the first side structure, and is at the same height as the support plate FBAR;

[0051] The first side structure PaTa includes a plurality of first transistor control structures TR1 stacked up and down, and adjacent first transistor control structures TR1 are isolated by a first isolation layer 1201;

[0052] The second side structure PaTb includes a plurality of second transistor con...

Embodiment 2

[0071] Such as Figure 5 As shown, in a preferred embodiment, a method for preparing a three-dimensional stacked flash memory structure is also proposed, and the structure formed in each step can be as follows Figure 6-11 As shown, among others, can include:

[0072] Step S1, providing a substrate pre-preparation layer;

[0073] Step S2, using an etching process to etch the substrate pre-preparation layer along a first direction and using an insulator to perform a planarization process, so as to form a plurality of substrate pre-preparation layers extending along the first direction X and distributed at intervals Element forming interval PFA;

[0074] Step S3, etching the upper surface of the substrate preparation layer to form a plurality of grooves extending along a second direction Y different from the first direction X in the substrate preparation layer, so as to form a groove between every two grooves. A support plate FBAR, and a substrate 100 forming below ...

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PUM

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Abstract

The present invention relates to the field of semiconductor technology, in particular to a three-dimensional stacked flash memory structure, comprising: a substrate; a support plate formed on the upper surface of the substrate and made of semiconductor materials; a first side structure; a second side structure; a first side The structure includes a plurality of first transistor control structures stacked up and down, and adjacent first transistor control structures are isolated by a first isolation layer; the second side structure includes a plurality of second transistor control structures stacked up and down, and Adjacent second transistor control structures are isolated by a second isolation layer; each first transistor control structure forms multiple first transistors connected to the support plate; each second transistor control structure forms multiple first transistors connected to the support plate A second transistor; can form a three-dimensional stacked flash memory structure, can minimize the layout area of ​​the transistor column, and at the same time fully expand the length of the transmission channel of the transistor to greatly improve the storage performance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a three-dimensional stacked flash memory structure and a preparation method thereof. Background technique [0002] Nand flash memory chip is a non-volatile memory device. Such as figure 1 As shown, it contains multiple unit strings, that is, the transistor column STG<1>~STG <m>Array of strings arranged, ie transistor array STARR. Each transistor column STG<1>~STG <m>From the corresponding bit line BL<1>~BL <m>The drain selection transistor DST connected in series with the common power supply line CSL, and the plurality of cell transistors MC<1> to MC <n>And source select transistor SST composition. At this time, the drain selection transistor DST, the multiple cell transistors MC<1>~MC <n>and the source selection transistor SST are respectively attached with the drain XDS selection signal, and the correspon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11578H10B43/20
CPCH10B43/20
Inventor 金鎭湖康太京
Owner DOSILICON CO LTD