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Method for eliminating multi-plane programming failure of TLC flash

A programming failure, flash memory technology, applied in the storage field, can solve problems such as programming failure, and achieve the effect of ensuring correctness

Inactive Publication Date: 2018-09-18
SHENZHEN YILIAN INFORMATION SYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] For the above defects, the purpose of the present invention is how to solve the problem that when a bad block occurs in multi-chip parallel programming, programming failures also occur in other normal blocks of parallel programming.

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  • Method for eliminating multi-plane programming failure of TLC flash
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  • Method for eliminating multi-plane programming failure of TLC flash

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Embodiment Construction

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0017] The multi-chip programming function of TLC can effectively improve the write performance of SSD, so SSD must use this function, so the firmware needs to take some special processing to solve the defect of multi-chip programming. As mentioned above, this defect occurs when the physical page happens to be in a bad block. The probability of this happening in practical applications is very small, so it basically does not affect the performance during normal use. ...

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Abstract

The invention discloses a method for eliminating multi-plane programming failure of a TLC flash. The method is characterized by comprising the steps of taking pre-allocated blocks in the TLC flash ascache blocks; forcedly converting the cache blocks to be in an SLC mode; writing data written in a host in the cache blocks firstly; enabling a multi-plane parallel writing mode by a background of a hard disk controller when a system is idle, thereby performing parallel writing on the data in the cache blocks; when a plane has a writing error, adding operation of checking the correctness of otherblock data written in parallel when the error occurs after the writing is finished; and if the error occurs, obtaining correct data from the cache blocks again, and performing rewriting. By opening upa part of the SLC blocks as a flash cache, the host data is written in the SLC blocks firstly, then when an SSD is idle, firmware enables multi-plane programming for writing the data in the SLC cachein the TLC blocks, and if the multi-plane programming fails, the source data in the SLC cache can be rewritten in a new physical address; and the technology can ensure the correctness of the data written in the flash, and the host performance is not influenced.

Description

technical field [0001] The invention relates to the technical field of storage, in particular to a method for eliminating multi-chip programming failure of TLC flash memory. Background technique [0002] Common flash memory (Nand Flash) has only one chip (chip) inside, and each chip has only one plane (plane), while some complex flash memory with larger capacity has multiple chips inside, and each chip has multiple planes. ,Such as figure 1 shown. This type of flash memory often has more advanced functions, such as multi-plane programming (Multi Plane Program) function. [0003] The chip execution command of the flash memory is serial, that is, only one command (read, write or erase) can be executed each time. In order to improve the performance of the large-capacity flash memory (this patent refers to the case of packaging multiple planes in a single chip), Particle manufacturers provide multi-chip (take 2 plane as an example in this patent) programming interface, such a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G06F12/02
CPCG06F11/1048G06F11/1068G06F12/0246
Inventor 许毅吴娴
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD