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Method and device for data multiplexing and synchronization in coarse-grained data flow architecture

A technology of data multiplexing and data flow, applied in the direction of electrical digital data processing, program code conversion, instruments, etc., can solve the problem of not being able to fully utilize the performance of the processor core, and achieve the effect of reducing work and efficient program operation

Active Publication Date: 2021-06-25
上海睿伍科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The realization of this coarse-grained data flow structure requires real-time scheduling of program blocks through the task scheduling module, and the maintenance of data dependencies in the data flow graph, which makes the processor core may be idle for a lot of time, especially for the processor When the size of the core is very large, scheduling by only one or a few task scheduling modules often cannot make full use of the performance of the processor core

Method used

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  • Method and device for data multiplexing and synchronization in coarse-grained data flow architecture
  • Method and device for data multiplexing and synchronization in coarse-grained data flow architecture
  • Method and device for data multiplexing and synchronization in coarse-grained data flow architecture

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Embodiment 1

[0043] To realize the data multiplexing and synchronization mechanism, it is necessary to add special instructions, and insert special instructions in the code according to the rules; and it is necessary to add logic to the hardware structure: add a synchronization control table to each processor core, and add special instruction decoding and Launch control logic.

[0044] 1. Data multiplexing and synchronization instructions

[0045] In order to achieve data multiplexing and synchronization in the coarse-grained data flow architecture, we added two instructions, copy instruction (COPY) and synchronization instruction (ACK). The COPY instruction is used to transfer the data acquired or calculated by this program block to other program blocks. The format of the COPY instruction is shown in Table 1 below, which includes the data to be transferred, the id of the program block (program block) to which the data is to be sent, the id of the processor core (Core) where the program blo...

Embodiment 2

[0058] The data multiplexing and synchronization process will be described in detail below with a specific embodiment.

[0059] We assume that there are two program blocks program block0 and program block2 on Core0; there are two program blocks program block1 and program block3 on Core1. Among them, program block0 has two child nodes, and programblock1 has one child node, such as Figure 4 shown.

[0060] Suppose there are 4 COPY instructions in program block0 and program block1, which are:

[0061] Program block0:

[0062] Program block1:

[0063] Correspondingly, there will be three ACK instructions in program block2 and program block3:

[0064] Program block2: ACK00

[0065] Program block3:

[0066] 1. In the initial state, you need to configure the parent program block and COPY_COUNT in the monitor, and ACK_COUNTER in the synchronization control table. At the same time, set the receive count in the COPY table of the monitor to 0, set all receive to 0, and al...

Embodiment 3

[0085] In yet another specific embodiment, the technical solution of the present invention may also appear in the form of a device or system, which may include a single processor core or multiple processor cores, either in The copy control and synchronization control between data blocks in a single processor can also be used for copy control and synchronization control between data blocks in a multi-processor system.

[0086] In addition, it should be pointed out that the preferred technical solution in Embodiment 3 may be combined with methods or algorithms used in other embodiments.

[0087] The device includes at least one processor, and the processor includes a copy instruction decoding and operation module, a synchronization instruction decoding and operation module, and a monitor module;

[0088] The copy instruction decoding and operation module is used for adding a copy instruction in the program block where the data to be used is located when the data in a program blo...

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Abstract

The present invention provides a method and device for data multiplexing and synchronization in a coarse-grained data flow architecture. When the data in a program block in the device needs to be used by other program blocks, a copy instruction is added to the program block where the data to be used is located, and a logical operation for the copy instruction; synchronous instruction decoding and operation modules, It is used to add synchronization instructions to the program block when the number of copy instructions pointing to the same program block is greater than 1, and is used for the logical operation of the synchronization instructions; the monitor module is used to monitor the number of copy instruction packets received by each program block quantity. This solution can automatically perform data multiplexing and synchronization operations between program blocks, reduces the work of the task scheduling module, and makes the programs in the data flow architecture run more efficiently.

Description

technical field [0001] The invention relates to the field of computer architecture, in particular to a method and device for coarse-grained data multiplexing and synchronization in a data flow framework. Background technique [0002] The coarse-grained data flow architecture mainly implements data dependency and program block scheduling between processor cores through a programming model. In the coarse-grained data flow structure, the program is divided into multiple program blocks, and the dependencies between the program blocks are established through data correlation, and different data blocks constitute the data flow graph. The coarse-grained data flow architecture schedules the program blocks that meet the dependency conditions to the idle processor cores through the task scheduling module. After the program blocks are executed, the data dependencies in the data flow graph are updated, and new executable program blocks are scheduled. Execute on an idle processor core. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/41
CPCG06F8/454
Inventor 向陶然严明玉谭旭叶笑春范东睿王达
Owner 上海睿伍科技有限公司