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System level chip evaluation device and method

A system-level chip and chip technology, applied in the direction of measurement devices, automated test systems, measurement electronics, etc., can solve problems such as one-sided testing

Inactive Publication Date: 2018-09-28
CHINA ELECTRONICS PROD RELIABILITY & ENVIRONMENTAL TESTING RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The SoC chip is composed of millions or even hundreds of millions of components, and has a system clock frequency of up to hundreds of MHz or even GHz. The chip needs to realize a variety of functions, and there are intricate timing relationships within and between modules. Most of them use deep Sub-micron process technology, these characteristics of SoC chips bring challenges to its testing work
Traditional SoC chip testing is limited by hardware conditions, and the chip testing carried out on it has the problem of one-sided testing, which cannot well realize the chip testing of SoC chips.

Method used

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Embodiment Construction

[0030] A system-level chip evaluation device, such as figure 1 As shown, including ATE test board 100, SoC system verification board 200 and controller 300, ATE test board 100 and SoC system verification board 200 are connected with controller 300 respectively; Controller 300 controls ATE test board 100 to obtain the system-on-chip under test Control the SoC system verification board 200 to obtain the application-level data of the system-level chip under test, and obtain the evaluation result of the system-level chip under test according to the parameter-level data and application-level data of the system-level chip under test.

[0031] The ATE test board 100 is used to acquire parameter-level data of the SoC under test. Parameter-level data refers to the data obtained by testing parameters related to SoC chip interface characteristics, including DC parameters, AC parameters, etc., and specific tests are completed under different voltage, current, frequency and load conditions...

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Abstract

The invention relates to a system level chip evaluation device and method. The device comprises an ATE test board, an SoC system verification board and a controller, wherein the controller controls the ATE test board to obtain parameter level data of a system-on-chip to be tested, and controls the SoC system verification board to obtain application level data of the system-on-chip to be tested, and obtains the evaluation result of the system-on-chip to be tested according to the parameter level data and the application level data of the system-on-chip to be tested. The parameter level test ofthe system-on-chip to be tested be realized, the application level test of the system-on-chip to be tested can be realized, and the performance test of the SoC chip can be performed more comprehensively and systematically, thereby obtaining a more comprehensive evaluation result, reducing the dependence of the SoC chip testing on automated test equipment, and significantly reducing the huge cost due to hardware upgrade of the automated test equipment.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a system-level chip evaluation device and method. Background technique [0002] With the rapid development of integrated circuits, SoC (System on Chip, system-on-chip / system-on-chip) chips are increasingly widely used, especially in the fields of high performance, low power consumption and miniaturization of electronic consumer products. SoC technology integrates digital, analog, radio frequency and corresponding interface modules through IP (Intellectual Property, intellectual property) core multiplexing, making full use of existing design accumulation, and reducing power consumption, reducing area, and increasing system functions It has obvious advantages in terms of improving speed and saving costs. [0003] In the manufacturing process of SoC chips, any slight process error and change will cause defects in the chip, making the chip unable to work normally. The test res...

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2834G01R31/2884G01R31/2886G01R31/2889
Inventor 王小强罗军唐锐李军求孙宇
Owner CHINA ELECTRONICS PROD RELIABILITY & ENVIRONMENTAL TESTING RES INST
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