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IGBT chip with folding-type composite gate structure

A compound gate, folded technology, applied in the direction of electrical components, circuits, semiconductor devices, etc., to achieve the effect of retaining low and high plane gate width safe working area and retaining power consumption

Active Publication Date: 2018-09-28
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] figure 2 and image 3 The bottom of the trench gate has a certain limit on the resistance capacity of the IGBT chip
its with figure 1 Compared with the IGBT chip with a planar gate structure shown in the figure, while improving the performance of the IGBT chip, it also sacrifices part of the withstand voltage and solid performance of the planar gate.

Method used

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  • IGBT chip with folding-type composite gate structure
  • IGBT chip with folding-type composite gate structure
  • IGBT chip with folding-type composite gate structure

Examples

Experimental program
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Embodiment Construction

[0038] The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings and examples, so as to fully understand and implement the process of how to apply technical means to solve technical problems and achieve technical effects in the present invention. It should be noted that, as long as there is no conflict, each embodiment and each feature in each embodiment of the present invention can be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.

[0039] Figure 4 It is a schematic top view of an IGBT chip hexagonal cell with a folded composite gate structure in an embodiment of the present invention. Such as Figure 4 As shown, each cell 410 is a hexagonal cell structure, and a plurality of cells are distributed on the wafer substrate in a honeycomb shape. Wherein, each cell 410 includes a gate region 401 and trench gate active regions 402 and plan...

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PUM

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Abstract

The invention discloses an IGBT chip with a folding-type composite gate structure, and the IGBT chip comprises a plurality of composite gate units, wherein each of the composite gate units comprises agate region and active regions located at both sides of the gate region, the gate region includes at least one trench formed by downward etching at a specified position of the gate region, and the interior of the trench is provided with a trench gate; a plane gate on a surface of the gate region, wherein the plane gate is connected with the trench gate. Each active region includes a trench gate active region and a plane gate active region, which are respectively located at two sides of the gate region, and each of the trench gate active region and the plane gate active region includes an N well region, a P well region, a P+ doped region and an N+ doped diffusion region from the bottom to the top. The IGBT chip can greatly increase the density of = IGBT chips, and maintains the characteristics that the trench gate is low in low-pass consumption and is high in current density and the plane gate is wide in safety work region.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an IGBT chip with a folded composite gate structure. Background technique [0002] Since the advent of IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) devices around 1980, due to the characteristics of bipolar transistor on-state voltage drop and high current density, and MOSFET (Metal-Oxide-Semiconductor Field -Effect Transistor, Metal-Oxide Semiconductor Field Effect Transistor) has high input impedance and fast response, and is widely used in rail transit, smart grid, industrial frequency conversion and new energy development and other fields. [0003] figure 1 It is a schematic cross-sectional view of a half cell of an IGBT chip with a planar gate structure in the prior art. Such as figure 1 As shown, it mainly includes: substrate 101, N well region 102, P well region 103, N+ doped region 104, P+ doped region 105, planar gate 106, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/739H01L29/423H01L29/06
CPCH01L29/0603H01L29/0684H01L29/423H01L29/7393H01L29/0653H01L29/0696H01L29/404H01L29/407H01L29/417H01L29/42376H01L29/66348H01L29/7395H01L29/7396H01L29/7397H01L29/41766H01L29/42356H01L29/4236
Inventor 刘国友朱春林朱利恒
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD