CPLD-based method for automatically adjusting high-speed pulse output duty ratio

Abstract

The invention discloses a CPLD-based method for automatically adjusting a high-speed pulse output duty ratio. A needed frequency value and duty ratio value are inputted into an MCU; the MCU transmitsthe values to a high-speed pulse output EBRSRAM block; the high-speed pulse output EBRSRAM transmits the values to an MOS tube output module continuously, so that the MOS tube works based on designated values; when the MOS tube works, the MOS tube output module outputs the frequency value and duty ratio value in working in real time and transmits the values to a high-speed pulse output feedback EBRSRAM block; and the high-speed pulse output feedback EBRSRAM block feeds back the data to a frequency and duty ratio state machine. The CPLD-based method for automatically adjusting a high-speed pulse output duty ratio belongs to the field of industrial automation technology. With the method disclosed by the invention, work can be interrupted timely and adjustment can be carried out timely; and aproblem of a large offset between the duty ratio of the high-speed pulse output outputted finally and a preset value because of junction capacitance of the MOS tube is solved.

Description

technical field [0001] The invention relates to the technical field of industrial automation, in particular to a method for automatically adjusting the duty ratio of high-speed pulse output based on CPLD. Background technique [0002] A PLC (Programmable Logic Controller) is a numerically-operated electronic system specially designed for use in industrial environments. It uses a programmable memory to store instructions for performing logic operations, sequence control, timing, counting, and arithmetic operations, and controls various types of mechanical equipment or production through digital or analog input and output. process. Widely used in various automation control fields, one of the main functions of PLC is to realize high-speed pulse output with different frequency and duty cycle. [0003] In order to realize the high-speed pulse output of PLC, currently many CPLDs are used to realize it. Multiple output pulse frequency and duty ratio registers are set in the CPLD,...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the deficiencies in the prior art, the present invention provides a method for automatically adjusting the duty cycle of high-speed pulse output based on CPLD, which solves the problem of the junction capacitance of the MOS tube, which causes the duty cycle of the final output high-speed pulse output to be different from the preset one. There is a large deviation in the set value, and a large number of registers are set at the same time, which will consume a lot of CPLD lookup table resources.

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