Mask for integrated circuit development

Abstract

The present invention provides a mask for integrated circuit development, which comprises a graphics area and a non-graphics area, wherein the graphics area comprises a first graphics area and a second graphics area outside the first graphics area; a light shielding strip is disposed between the first graphics area and the second graphics area; a first cutting channel is added to the light shielding strip, the non-graphics area is provided with a second cutting channel, and overlay marks are arranged on the first cutting channel and the second cutting channel. The mask for integrated circuit development in the invention has the beneficial effects: the OPC graphics area and other graphics areas can be exposed according to research and development requirements, thereby effectively avoiding the interference of photoresist residue on the OPC graphics area on other graphics areas, and ensuring normal achievement of each graphics area.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a mask plate for research and development of integrated circuits. Background technique [0002] With the development of integrated circuit manufacturing technology towards higher integration and smaller feature size, photolithography technology has become a key factor limiting the development of integrated circuits to smaller feature sizes. The main task of the photolithography process is to transfer the design layout of the integrated circuit from the mask plate to the surface of the silicon wafer. However, with the reduction of the feature size, the interference and diffraction effects of light make there is a big difference between the actual pattern produced by lithography on the silicon wafer and the ideal pattern of the design layout, and the mask pattern transfer is distorted, thus affecting to circuit performance and yield. [0003] Optical Proximity Corr...

AI Technical Summary

Problems solved by technology

However, the graphics in the OPC graphics area that violate the design rules will cause photoresist residue and transfer defects on the silicon wafer after photolithography, which will interfere or even destroy the performance test of other graphics areas on the silicon wafer.

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