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Method and device for shortening SSD response delay

A response delay and data technology, applied in the field of SSD reading and writing, can solve the problem of affecting the response delay of read commands, and achieve the effect of reducing command response delay time, improving data transmission efficiency, and reducing data transmission time.

Inactive Publication Date: 2018-11-06
SHENZHEN YILIAN INFORMATION SYST CO LTD
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the promotion of enterprise-level applications, the tR of some NAND will be very short, such as Toshiba's XL Flash, its tR is only about 8us, so the serial transmission method will greatly affect the read command response delay

Method used

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  • Method and device for shortening SSD response delay
  • Method and device for shortening SSD response delay
  • Method and device for shortening SSD response delay

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Embodiment Construction

[0054] In order to illustrate the idea and purpose of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0055] LPA: Fragmentation unit.

[0056] LBA: sector.

[0057] PPA: physical address.

[0058] refer to Figure 1-Figure 4 , a specific embodiment of the present invention proposes a method for improving SSD response delay, which specifically includes the following steps,

[0059] S10. Initiate a request to write 4KB data.

[0060] S20. Divide the 4KB data into multiple slice units, and write them into different NAND DIEs.

[0061] S30. Update the physical address-to-mapping table corresponding to the fragmentation unit.

[0062] S40. Initiate a request to read 4KB data.

[0063] S50. Concurrently read data from corresponding NAND DIEs according to the physical addresses in the mapping table.

[0064] For step S10, the process of writing data into the SSD is as follows...

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Abstract

The invention discloses a method and a device for shortening SSD response delay. The method comprises the steps that a 4KB data writing request is initiated; 4KB data is divided into multiple slice units and written into different NAND DIEs; physical addresses corresponding to the slice units are updated to a mapping table; a 4KB data reading request is initiated; and the data is concurrently readfrom the corresponding NAND DIEs according to the physical addresses in the mapping table. According to the scheme, a variable slicing strategy is adopted, and the 4KB data is divided into multiple parts and written into the different NAND DIEs; and when a host reads the corresponding 4KB data, the data is concurrently transmitted from the corresponding NAND DIEs, so that data transmission time is shortened. Therefore, response delay time of an SSD data reading command is shortened, and data transmission efficiency is improved.

Description

technical field [0001] The present invention relates to the field of SSD reading and writing, in particular to a method and device for improving SSD response delay. Background technique [0002] In existing SSD application systems, 4KB mapping is generally used. For the data written by the host, the SSD internally divides the data blocks into 4KB units and assigns physical addresses, and maintains a mapping table in the memory to track the logical-to-physical conversion relationship. [0003] Based on this factor, 4KB-aligned user data necessarily falls on unique physical blocks. When the host accesses this data, it needs to trigger NAND reading (tR) and NAND data transmission (tXfer) in sequence. [0004] The read (tR) of traditional NAND is about 50us, and the data transfer (tXfer) is about 8.8us. In this case, the system response delay is mainly determined by tR. With the promotion of enterprise-level applications, the tR of some NAND will be very short, such as Toshib...

Claims

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Application Information

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IPC IPC(8): G06F3/06
CPCG06F3/0611G06F3/0638G06F3/0644G06F3/0679
Inventor 王猛王伟良徐伟华
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD