Interrupt operation method of tte end system adapter card pcie controller

Abstract

The invention discloses an interrupt operation method of a TTE terminal system adapter card PCIe controller, which is used to solve the problem in the prior art that data is overflowed and lost due to insufficient adapter card buffer space due to a read interrupt initiated by a host. The technical solution is: 1) requesting to read and write data; 2) periodically requesting to read and write data to the PCIe bus controller; 3) the PCIe bus controller generates an interrupt sequence and configures the read and write cache registers; 4) the PCIe driver Identify the interrupt type and determine the amount of data to be moved; 5) The PCIe driver configures the read and write related registers and starts the direct memory access operation to complete the data transfer and end the direct memory access operation. The present invention initiates direct memory access read and write operations through the adapter card to realize flow control. The present invention utilizes the adapter card to actively issue interrupts, which improves the time accuracy of the end system and can be used for time triggering in the adapter card of the Ethernet TTE end system. Interrupt module design.

Description

technical field [0001] The invention belongs to the technical field of communication, and in particular relates to an interrupt operation method of a PCIe controller interconnected with high-speed peripheral components, which can be used to time-trigger the design of an interrupt module in an adapter card of an Ethernet TTE end system, so as to ensure that data will not be buffered by the adapter card Area overflow and loss, and improve the time precision of the time-triggered Ethernet TTE end system. Background technique [0002] High-speed peripheral component interconnect PCIe is a high-speed serial transmission bus with point-to-point, dual-channel and high-bandwidth transmission characteristics. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. After the direct memory access DMA operation on the side of the board is completed, a read / write interrupt is generated through the PCIe bus controller to inform the board on the host...

AI Technical Summary

Problems solved by technology

[0004] First, after the host fills in the direct memory access DMA read and write related registers, when the board is moving data, the data will be lost due to the buffer overflow of the board, and flow control cannot be realized;

[0005] Second, the host, as the active party, fills in the direct memory access DMA to read and write related registers, and actively initiates data transmission operations. Due to the influence of the host operating system, its time accuracy is far inferior to that of the board card actively initiating data transmission operations.

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