e-fuse storage array, e-fuse and e-fuse operation method

Abstract

The invention provides an E-FUSE, an E-FUSE storage array, and an E-FUSE operation method, which belong to the technical field of integrated circuits, and include: N word lines arranged in a row direction, N programming signal lines arranged in a row direction, N bit lines arranged in the column direction, N source lines arranged in the column direction, and memory cells arranged in a matrix of N rows*N columns, the memory cells include gates, drains, and sources, and N is a positive integer; , the memory cell is a PMOS equivalent programming diode circuit; the gates of the memory cells in the same row are connected to the same word line, the N wells of the memory cells in the same row are connected to the same programming signal line, and each memory cell in the same column The drains of the cells are respectively connected to the same source line through fuse resistors, and the sources of the memory cells in the same column are connected to the same bit line. The beneficial effect of the present invention is that there is no need to use the small-sized NMOS programming selection drive tube in the Deep NW, and the layout area of ​​the E-FUSE storage unit is small.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an E-FUSE, an E-FUSE storage array and an E-FUSE operation method. Background technique [0002] E-fuse technology is mainly developed based on the theory of electromigration. The E-fuse circuit designed by using this principle can realize the redundant function of the SRAM circuit part in the chip, and can also realize the electronic chip identity authentication (Electronic Chip ID-ECID ) and other functions, greatly improving the intelligence of the chip. [0003] During the programming operation, the traditional E-fuse memory cell structure, such as the NMOS substrate (P-Well) of the E-FUSE memory cell with NMOS equivalent programming diode circuit, is connected to the potential of the programming voltage (VCC), so each All memory cells need to use n-deep well (Deep N-Well, DNW) to isolate the high potential VCC, which increases the layout area of ​​the memory cel...

AI Technical Summary

Problems solved by technology

[0003] During the programming operation, the traditional E-fuse memory cell structure, such as the NMOS substrate (P-Well) of the E-FUSE memory cell with NMOS equivalent programming diode circuit, is connected to the potential of the programming voltage (VCC), so each All memory cells need to use n-deep well (Deep N-Well, DNW) to isolate the high potential VCC, which increases the layout area of ​​the memory cell (cell)

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