3D memory device and manufacturing method thereof

Abstract

The application discloses a 3D storage device and a manufacturing method thereof. The 3D memory device includes: a substrate; a stacked structure located above the substrate, the stacked structure including multiple gate conductors and multiple interlayer insulating layers stacked alternately; multiple channel pillars running through the stacked structure; and The conductive channel runs through the stacked structure, and the conductive channel is connected to the bottom ends of the plurality of channel columns through the substrate, wherein the upper part of the conductive channel includes the conductive column, and the lower part includes the insulating core and the conductive layer surrounding the insulating core. By making the insulating core at the lower part of the conductive channel and adjusting the ratio of the insulating core to the conductive column occupying the conductive channel, the purpose of adjusting the warpage of the wafer from positive to negative can be achieved.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and manufacturing methods thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared w...

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Problems solved by technology

However, the conductive path will have an impact on the wafer bow, which is high in the prior art and cannot change the wafer bow variable (wafer△bow)

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