A method for realizing a multi-sampling rate ADC controller

Abstract

The invention discloses a method for realizing a multi-sampling rate ADC controller. A sampling trigger pulse is independently generated by each sampling controller through a triggering timer, and then the sampling trigger combiner combines the sampling trigger signals of multiple channels to form a sampling trigger signal with varying intervals to start the ADC module, finally, the sampling valuedistributor synchronously writes the ADC conversion result into the sampling value buffer queue of the corresponding sampling controller according to the sampling trigger request of each independentsampling controller to complete multi-rate data sampling, The invention has the advantages of simple and easy realization, small sampling buffer, few ADC starting times, short sampling delay and the like, and has a good application prospect.

Description

technical field [0001] The invention relates to the technical field of data acquisition, in particular to a method for realizing an ADC controller with multiple sampling rates. Background technique [0002] With the rapid development of microprocessor technology, in the current embedded device applications, there are requirements for multiple microprocessors to cooperate to complete system functions. Due to the size, cost, power consumption and other factors of embedded devices, more expectations The data collected by the front end can realize multi-service sharing. However, since the focus of each application program is different, the sampling rate requirements are also different, so the sampling rate conversion has become a problem that many real-time embedded device applications have to face. In the prior art, the sampling rate conversion of analog data , there are mainly the following two methods, as follows: [0003] (1) High-speed sampling is performed according to t...

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Problems solved by technology

[0005] The above two methods have achieved multi-rate sampling to a certain extent, and there are different defects, as follows: method (1) requires ADC high-speed sampling and requires a large amount of buffer, and because the ADC works in high-speed mode, the system power consumption will also be proportional increase; method (2) uses the interpolation method to realize the sampling rate conversion, but it will bring additional processing delay and a large amount of calculation overhead to the data acquisition system. In addition, the low-order interpolation algorithm will also cause high-frequency The component is attenuated, the output accuracy is reduced, and the noise is inevitably introduced by the algorithm

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