High radix subset code multiplier architecture

A technology of multipliers and subsets, applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of not so efficient, expensive soft multipliers, consuming integrated circuit area, power, routing and/or Packaging resources and other issues to achieve the effects of reduced power consumption, low latency, and improved routability

Pending Publication Date: 2018-12-28
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, however, soft multipliers can be very expensive to use
Soft multipliers consume significant area, power, routing, and / or packaging resources of an integrated circuit, and as such, they are not as efficient for use in machine learning applications

Method used

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  • High radix subset code multiplier architecture
  • High radix subset code multiplier architecture
  • High radix subset code multiplier architecture

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Embodiment Construction

[0019] While one or more specific embodiments are described below, in an attempt to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, several implementation-specific decisions may be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, This may vary by implementation. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, manufacture, and fabrication for those of ordinary skill having the benefit of this disclosure.

[0020] As described in further detail below, embodiments of the present disclosure generally relate to circuits for enhancing soft multipliers implemented on integrated circuits (ICs). ...

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Abstract

Systems, methods, and devices for enhancing performance / efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.

Description

[0001] Cross References to Related Applications [0002] This application is a non-provisional application claiming priority to U.S. Provisional Patent Application No. 62 / 522,546, entitled "High Radix Subset Code Multiplier Architecture," filed June 20, 2017, which is incorporated herein by reference. technical field [0003] The present disclosure relates generally to integrated circuits, such as Field Programmable Gate Arrays (FPGAs). More specifically, the present disclosure relates to soft multiplier logic implemented on integrated circuits (eg, FPGAs). Background technique [0004] This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure that are described and / or claimed below. This discussion is considered helpful in providing the reader with background information used to facilitate a better understanding of various aspects of the disclosure. Accordingly, it should be understood that ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/491
CPCG06F7/4915G06F7/5336G06F7/523G06F2207/4812G06F7/4824
Inventor M·朗哈默尔G·贝克勒
Owner INTEL CORP
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