A Realization Method of Fractional Frequency Division with Dithering Mechanism

A technology of fractional frequency division and realization method, applied in the direction of automatic power control, electrical components, etc., can solve the problems of high cost, influence wide application, complex structure of interpolation circuit, etc., and achieve the effect of easy debugging and low cost

Active Publication Date: 2022-07-19
浙江芯劢微电子股份有限公司
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Problems solved by technology

API (analog phase interpolation) technology is usually used to eliminate this spurious phase modulation to improve the spectral purity of the fractional frequency phase-locked loop output signal, but because this method requires the use of more analog devices, the interpolation circuit structure is complex, High cost and difficult debugging, thus affecting its wide application

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  • A Realization Method of Fractional Frequency Division with Dithering Mechanism
  • A Realization Method of Fractional Frequency Division with Dithering Mechanism
  • A Realization Method of Fractional Frequency Division with Dithering Mechanism

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specific Embodiment

[0029] like Figure 1-8 Shown is a specific embodiment of the present invention, which is a method for realizing fractional frequency division with a jittering mechanism, and the method includes the following steps:

[0030] Step 1): Generate a 18-bit pseudo-random signal through a pseudo-random signal generator based on the 18-bit Linear Feedback Shift Register (LFSR) principle, and then send the pseudo-random signal into a first-order delta-sigmal modulator for quantization noise shaping to a high value. The first-order delta-sigmal modulator is composed of an 18-bit accumulator, and the first-order delta-sigmal modulator realizes the structure as follows Figure 4 As shown in the figure, its function is to perform noise shaping on the 18-bit pseudo-random signal to reduce low-frequency noise, and at the same time convert the jittered signal into 1 bit, and perform low-bit jittering on the fractional frequency division parameter signal, which reduces the system noise and doe...

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Abstract

The invention discloses a method for realizing fractional frequency division with a jittering mechanism, which belongs to radio communications and integrated circuits. Pseudo-random jittering signal based on LFSR) principle, generates 3-bit frequency division adjustment parameters through MASH 1‑1‑1 delta‑sigmal modulator, and adjusts the instantaneous frequency division coefficient to make the average frequency division ratio within a period of time as required The invention has the technical characteristics of low cost, simple debugging, adjustable instantaneous frequency division coefficient, arbitrarily small frequency interval, and frequency synthesis that can achieve high frequency resolution.

Description

technical field [0001] The invention relates to a method for realizing fractional frequency division, more specifically, to a method for realizing fractional frequency division with a jittering mechanism, which belongs to the fields of wireless communication and integrated circuits. Background technique [0002] In the prior art, frequency synthesis is generally divided into two types: one is a direct frequency synthesizer (DFS), the other is an indirect frequency synthesizer, which can be further divided into single-loop frequency synthesis (NFS), Synthesis (MNFS) and Fractional Frequency Synthesis (FNFS). [0003] The direct frequency synthesizer (DFS) uses full analog implementation. Although it has a high frequency conversion speed, with the reduction of the frequency interval, the number of components increases, the volume increases, and the cost increases greatly, and many unpredictable combinations are generated. frequency, the spectral purity is low. [0004] Altho...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/197
CPCH03L7/1974
Inventor 何利蓉肖文勇
Owner 浙江芯劢微电子股份有限公司
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