A data transmission system and a transmission method based on FPGA

Abstract

The invention discloses a data transmission system based on FPGA and a transmission method thereof. The PS module is arranged and a PL module comprising an SRIO module, an LVDS module and a PS module-PL module, a DMA module and a FIFO memory is also arranged, the SRIO module and the LVDS module are used to transmit and receive data, at that same time, the data is stored in the FIFO memory, the DMAmodule receives a PS module for accessing data in the FIFO memory, various control and data calculation are carried out within that PS module, while in the PL module, it is mainly used for data transmission and control, reduces the amount of logic control in the PL module, make the whole design clear and simple, DMA module is used to realize the data transmission between PS module and PL module,reducing consumption on the bus. With a burst of transmission like DMA, the number of initiation operations of the PS module is reduced, and the DMA transmission mode does not require the participation of the PS module in the data moving process, the PS module is free from the data move work, the program in the PS module is optimized, and more time is provided for data processing at the same time.

Description

technical field [0001] The invention belongs to the technical field of video signal data control design, and in particular relates to an FPGA-based data transmission system. Background technique [0002] For ordinary FPGAs (Field Programmable Gate Arrays), the pure logic structure makes FPGAs consume a lot of resources in floating-point operations. At present, in order to solve the problem of FPGA computing capabilities, Xilinx has launched the Zynq-7000 series of FPGAs, and the FPGA internal If the data transmission between the PS (Passive serial, passive serial loading method) module and the PL (Programmable Logic, programmable logic) module uses the traditional AXI bus to access the memory, the data transmission speed is low and the efficiency is low. The transmission method requires the PS module to initiate a transaction when accessing each address, thus reducing the data transmission speed. Contents of the invention [0003] The purpose of the present invention is t...

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Problems solved by technology

[0002] For ordinary FPGAs (Field Programmable Gate Arrays), the pure logic structure makes FPGAs consume a lot of resources in floating-point operations. At present, in order to solve the problem of FPGA computing capabilities, Xilinx has launched the Zynq-7000 series of FPGAs, and the FPGA internal If the data transmission between the PS (Passive serial, passive serial loading method) module and the PL (Programmable Logic, programmable logic) module uses the traditional AXI bus to access the memory, the data transmission speed is low and the efficiency is low. The transmission method requires the PS module to initiate a transaction when accessing each address, thus reducing the data transmission speed

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