A phase detector for preventing charge pump mismatch from limiting the pull-in range of a phase locked loop

Abstract

A phase detector is disclosed for preventing a charge pump mismatch from limiting the pull-in range of a phase locked loop, includes first and second NAND gates, first to tenth inverters, wherein a first input of the first NAND gate is connected with a reference clock, a second input of the first NAND gate is connected with an output of the second NAND gate, and a first input of the second NAND gate is connected with an output of the first NAND gate, and a second input of the second NAND gate is connected with a feedback clock; The output terminals of the first NAND gate are respectively connected with the input terminals of the first inverter and the third inverter, the first inverter is connected with the second inverter, and the output terminals of the second inverter, the input terminals of the fourth inverter and the output terminals of the fifth inverter are connected with nodes. The output terminal of the third inverter, the output terminal of the fourth inverter, and the inputterminal of the fifth inverter are connected to the node DN; An output terminal of the second NAND gate is connected to an input terminal of the sixth inverter and an input terminal of the eighth inverter. As that phase discrimination dead zone doe not exist in the present invention, the limitation of the pull-in range of the charge pump mismatched phase-locked loop can be eliminate.

Description

technical field [0001] The invention relates to a phase detector capable of resisting the limitation of the pull-in range of a phase-locked loop caused by charge pump mismatch, and belongs to the technical field of phase detectors. Background technique [0002] A phase detector (Phase Detector, referred to as PD) is an essential module of most phase-locked loop (Phase_Locked Loop, referred to as PLL) circuits. Through PD, the lead-lag relationship between the reference clock and the feedback clock is extracted, the oscillator is controlled after filtering, and finally the phase alignment of the reference clock and the feedback clock is realized to achieve the purpose of frequency locking. [0003] In recent years, applications such as high-speed interfaces have increasingly strong demands on wide-range PLLs. PLLs may face a wide range of frequency fluctuations during operation, which requires that the phase-locked loop has a sufficient pull-in range. The phase-locked loop b...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a phase detector that resists the limit of the pull-in range of the phase-locked loop caused by the mismatch of the charge pump, and solve the problem of charging by optimizing the output timing and transmission characteristics of the phase detector. The problem of the influence of pump mismatch on the pull-in range of the phase-locked loop, to avoid the loss of lock of the phase-locked loop under extreme conditions

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