Method and system for obtaining internal time delay step time of storage module

Abstract

The invention discloses a method and system for obtaining the internal time delay step time of a storage module, and belongs to the technical field of communication. The method comprises the steps that a control unit sends a clock signal to a storage unit in at least two different phases, and time delay processing is carried out on a signal input interface of the control unit to obtain two boundaries of the signal input interface; and the delay time of one time delay step is calculated according to the difference of the number of time delay steps between the two boundaries of the signal inputinterface. According to the invention, two corresponding boundaries of the signal input interface in different clock signal phases are obtained through adjusting the phase in which the control unit sends the clock signal to the storage unit and carrying out time delay processing on the signal input interface of the control unit, then the delay time of the single time delay step is calculated according to different numbers of time delay steps in different clock signal phases, thereby being convenient for adjusting the delay time of the control unit according to the actual calculated delay timeof the time delay steps.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a method and system for acquiring the internal delay time of a storage module. Background technique [0002] In the use of SDIO (Secure Digital Input and Output Card, secure digital input and output card) interface, as the frequency increases, the problem of SDIO stability is gradually exposed. In practical applications, such as: when the SDIO unit reads signals to the SOC chip, although the unit step length of the internal delay can be obtained according to the specifications of the SOC chip (System-on-a-Chip), it is not necessarily accurate , if the time length of the unit ladder is wrong, it will cause misleading when setting the register, and then affect the stability of the system during the signal reading process. However, it is currently impossible to measure the unit ladder of the registers inside the SOC chip. Contents of the invention [0003] Aiming ...

AI Technical Summary

Problems solved by technology

[0003] Aiming at the problem that it is currently impossible to measure the unit ladder of the registers inside the SOC chip, a method and system for obtaining the internal delay ladder time of the storage module are now provided

Images