Bus interface system

Abstract

The invention provides a bus interface system, which is based on the existing AXI bus interface system. In the bus interface system, an AXI transmission channel for buffering Valid signal and / or dataand Ready signal is provided. In practice, when the AXI bus trace is too long or the load is too heavy, the transmission delay of Valid signal, data and Ready signal will be too large, which will leadto the timing non-convergence of AXI bus. In the invention, when the signal delay of the AXI bus is too large, the AXI transmission channel is used for buffering the Valid signal, the data and the Ready signal, so that the path with tight timing can be divided, the timing of the AXI bus can be optimized, and an interface system with correct function and timing convergence can be obtained.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to an AXI bus interface system. Background technique [0002] AXI (Advanced eXtensible Interface, advanced extensible interface) bus is widely used in SOC (System On a Chip, system integrated in one chip) chip, AXI bus contains 5 transmission channels, namely: read address channel, write address channel, Read data channel, write data channel and write response channel. Usually, several interfaces are mounted on the AXI bus, which can be divided into: a master interface (Master interface) and a slave interface (Slave interface), and each transmission channel between the master interface and the slave interface uses a handshake mechanism; The device can be connected to the corresponding interface when in use. [0003] In actual chip design, the AXI bus is usually routed in the gaps between multiple devices, and the devices are usually in different positions, resulting in the AXI...

AI Technical Summary

Problems solved by technology

[0003] In actual chip design, the AXI bus is usually routed in the gaps between multiple devices, and the devices are usually in different positions, resulting in the AXI bus needing to "shuttle" among multiple devices and hook up the devices. It is understandable Yes, this will cause the AXI bus to become longer, which in turn will cause the transmission delay of the AXI bus to become larger; secondly, when one more device is hung on the AXI bus, it is equivalent to adding a capacitive load to the AXI bus, which will further increase transmission delay

It is understandable that as the propagation delay increases, timing non-convergence problems may occur

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